2018 Microchip Technology Inc. DS70005340A-page 93
CAN FD Protocol Module
10.1.4 TEF STATUS FLAGS
There are four TEF status flags:
• TEFFIF: TEF Full Interrupt Flag; set when the TEF is full.
• TEFHIF: TEF Half Full Interrupt Flag; set when the TEF is at least half full.
• TEFNEIF: TEF Not Empty Interrupt Flag; set when there is at least one message in the TEF.
• TEFOVIF: TEF Overrun Interrupt Flag; set when overflow has occurred.
The status flags of the TEF are set when there are transmitted messages in the FIFO. Before the
first message is stored (after the TEF is reset), all status flags are cleared. When the TEF is full,
all flags are set.
10.2 Transmit FIFO Behavior
FIFO 1 is configured as a TX FIFO. C1FIFOCON1L and C1FIFOCON1H are used to control the
FIFO. C1FIFOSTA1 contains the status flags and the FIFO Index bits (FIFOCI<4:0>).
C1FIFOUA1L and C1FIFOUA1H contain the user address of the next transmit message object
to be loaded.
Figure 10-1 through Figure 10-6 illustrate how the status flags, user address and FIFO index are
updated for FIFO 1.
Figure 10-1 shows the status of FIFO 1 after Reset. Message objects, MO0 to MO4, are empty.
All status flags are set. The user address and the FIFO index point to MO0.
Figure 10-1: FIFO 1 – Initial State
Figure 10-2 illustrates the status of FIFO 1 after the first message (MSG0) is loaded. MO0 now
contains MSG0. The user application sets the UINC bit (C1FIFOCON1L<8>), which causes the
FIFO head to advance. The user address now points to MO1. TFEIF is cleared since the FIFO
is no longer empty. The user application now sets TXREQ to request the transmission of MSG0.
Figure 10-2: FIFO 1 – First Message Loaded
MO0
MO1
MO2
MO3
MO4
C1FIFOUA1L = 0x1D0
C1FIFOSTA1:
FIFOCIx = 0
TFEIF = 1
TFHIF = 1
TFNIF = 1
C1FIFOCON1L:
TXREQ = 0
MO0/MSG0
MO1
MO2
MO3
MO4
C1FIFOUA1L = 0x218
C1FIFOSTA1:
FIFOCIx = 0
TFEIF = 0
TFHIF = 1
TFNIF = 1
C1FIFOCON1L:
TXREQ = 1
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