Microchip Technology dsPIC33 series User Manual

 2018 Microchip Technology Inc. DS70005340A-page 59
CAN FD Protocol Module
5.3 CAN FD Bit Time Configuration
In order to achieve higher bandwidth, bits in a CAN FD frame are transmitted with two different
bit rates:
• Nominal Bit Rate (NBR): Used during arbitration until the sample point of the BRS bit and
the sample point of the CRC delimiter reach the EOF
• Data Bit Rate (DBR): Used during the data and CRC field
NBR is limited by the propagation delay of the CAN network (see Section 5.3.2 “Propagation
Delay”). In the data phase, only one transmitter remains; therefore, the bit rate can be increased.
The transmitting node always compares the intended transmitted bits with the actual bits on the
CAN bus. The propagation delay in the data phase can be longer than the bit time. In this case,
the data bits are sampled at a Secondary Sample Point (SSP) (see Section 5.3.3 “Transmitter
Delay Compensation (TDC)”).
NBR is the number of bits per second during the arbitration phase. It is the inverse of the Nominal
Bit Time (NBT) (see Equation 5-1).
Equation 5-1: Nominal Bit Rate/Time
DBR is the number of bits per second during the data phase. It is the inverse of the Data Bit Time
(DBT) (see Equation 5-2).
Equation 5-2: Data Bit Rate/Time
The Baud Rate Prescaler (BRP) is used to divide the SYSCLK. The divided SYSCLK is used to
generate the bit times.
There are two prescalers: NBRP for the Nominal Bit Rate Prescaler and DBRP for the Data Bit
Rate Prescaler. The Time Quanta (NTQ and DTQ) are selected as shown in Equation 5-3 and
Equation 5-4.
Equation 5-3: Nominal Time Quanta
Equation 5-4: Data Time Quanta
CAN bit times have four segments, as specified in ISO11898-1:2015 (see Figure 5-1).
Synchronization Segment (SYNC) – Synchronizes the different nodes connected on the CAN
bus. A bit edge is expected to be within this segment. The Synchronization Segment is always
1T
Q .
Propagation Segment (PRSEG) – Compensates for the propagation delay on the bus. PRSEG
has to be longer than the maximum propagation delay.
Phase Segment 1 (PHSEG1) – Compensates for errors that may occur due to phase shifts in
the edges. The time segment may be automatically lengthened during resynchronization to
compensate for the phase shift.
NBR
1
NBT
-----------=
DBR
1
DBT
------------=
NTQ NBRP T
SYSCLK

NBRP
F
SYSCLK
--------------------------==
DTQ DBRP T
SYSCLK

DBRP
F
SYSCLK
--------------------------==

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English