dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 58 2018 Microchip Technology Inc.
5.2 CAN Configuration
The C1CONH/L registers contain several bits that can only be configured in Configuration mode.
5.2.1 ISO CRC ENABLE
The module supports ISO CRC (according to ISO11898-1:2015) and non-ISO CRC (see
Section 2.1 “ISO vs. NON-ISO CRC”). ISO CRC is enabled by setting the ISOCRCEN bit.
5.2.2 PROTOCOL EXCEPTION DISABLE
The negative edge between the FDF bit and the “reserved bit” in CAN FD frames is important
for the calculation of the transceiver delay, and for hard synchronization. Therefore, if the
“reserved bit” following the FDF bit is detected recessive, the CAN FD Protocol Module will treat
this as a form error. This is called, “Protocol Exception Event Detection Disabled”, and is
configured by setting the PXEDIS bit.
The Protocol Exception Event Detection Disabled can be enabled by clearing the PXEDIS bit. As
a reaction to the protocol exception event, the error counters are not changed, hard
synchronization is enabled, the module sends recessive bits and enters the bus integration state.
5.2.3 WAKE-UP FILTER – WFT<1:0>
The WAKFIL bit is used to enable/disable the low-pass filter on the CxRX pin. The filter is only
active during Sleep mode. The WFTx bits allow the configuration of different filter times.
5.2.4 RESTRICTION OF TRANSMISSION ATTEMPTS
ISO11898-1:2015 requires that frames that lost arbitration and are not Acknowledged, or are
destroyed by errors, are automatically retransmitted. Optionally, the number of retransmission
attempts can be limited.
When the RTXAT bit is set, retransmission attempts can be limited using the TXAT<1:0> bits in
the FIFO Control registers. If the RTXAT bit is clear, then the TXATx bits in the FIFO Control
register are ignored and the retransmission attempts are unlimited.
5.2.5 ERROR STATE INDICATOR (ESI) IN GATEWAY MODE
Normally, the ESI bit in a transmitted message reflects the error status of the CAN FD Protocol
Module. ESI is transmitted recessive when the module is error passive. In case the module is
used in a gateway application, there will be situations where the ESI bit in the message should
be transmitted recessive, even though the gateway module is error active. This can be
configured by setting the ESIGM bit.
5.2.6 MODE SELECTION IN CASE OF SYSTEM ERROR
The SERRLOM bit selects which mode the module will transition to in case of a system error. The
module can either transition to Restricted Operation mode or Listen Only mode.
5.2.7 RESERVING MESSAGE MEMORY FOR TXQ AND TEF
Setting the TXQEN bit will reserve RAM for the TXQ. If the TXQEN bit is cleared, then the TXQ
cannot be used.
Setting the STEF bit will reserve RAM for the TEF and all transmitted messages will be stored in
the TEF.
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