Microchip Technology dsPIC33 series User Manual

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 62  2018 Microchip Technology Inc.
5.3.3 TRANSMITTER DELAY COMPENSATION (TDC)
During the data phase of a CAN FD transmission, only one node is transmitting; the others are
receiving. Therefore, the propagation delay does not limit the maximum data rate.
When transmitting via pin CxTX, the CAN FD Protocol Module receives the transmitted data
from its local CAN transceiver via pin CxRX. The received data is delayed by the CAN
transceiver’s loop delay. In case this delay is greater than 1 + DTSEG1, a bit error would be
detected.
In order to enable a data phase bit time that is shorter than the transceiver loop delay, the
Transmitter Delay Compensation (TDC) is implemented. Instead of sampling after DTSEG1, a
Secondary Sample Point (SSP) is calculated and used for sampling during the data phase of a
CAN FD message.
Figure 5-3 illustrates how the transceiver loop delay is measured and Equation 5-10 shows how
the SSP is calculated.
Equation 5-10: Secondary Sample Point
Figure 5-3: Measurement of Transceiver Delay (TDCV)
5.3.4 SYNCHRONIZATION
To compensate for phase shifts between the oscillator frequencies of the nodes on the CAN bus,
each CAN controller must be able to synchronize to the relevant edge of the incoming signal.
The CAN controller expects an edge in the received signal to occur within the SYNC segment.
Only recessive-to-dominant edges are used for synchronization.
There are two mechanisms used for synchronization:
• Hard Synchronization – Forces the edge that has occurred to lie within the
SYNC segment. The bit time counter is restarted with SYNC.
• Resynchronization – If the edge falls outside the SYNC segment, PHSEG1 or PHSEG2
will be adjusted.
For a more detailed description of the CAN synchronization, please refer to ISO11898-1:2015.
SSP = TDCV<5:0> + TDCO<6:0>
CxTX
FDF res BRS ESI DLC
Arbitration Phase
Data
Phase
CxRX
Arbitration Phase
Data
Phase
Transmitter Delay
Start Stop
Transmitter
Delay
Measurement
TSEG1<4:0> (C1DBTCFGH<4:0>)
Secondary Sample Point (SSP)
FDF

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English