Microchip Technology dsPIC33 series User Manual

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 40  2018 Microchip Technology Inc.
Register 3-38: C1FIFOUAxH: CAN FIFO User Address Register x (x = 1 to 31) High
(1)
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA<31:24>
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 FIFOUA<31:16>: FIFO User Address bits
TXEN =
1 (FIFO configured as a transmit buffer):
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
Register 3-39: C1FIFOUAxL: CAN FIFO User Address Register x (x = 1 to 31) Low
(1)
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA<15:8>
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 FIFOUA<15:0>: FIFO User Address bits
TXEN =
1 (FIFO configured as a transmit buffer):
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English