Microchip Technology dsPIC33 series User Manual

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 106  2018 Microchip Technology Inc.
12.1 FIFO Individual Interrupts
C1FIFOCONxL contains the interrupt enable flags and C1FIFOSTAx contains the interrupt flags
for the FIFOs. There is a separate register for each FIFO.
12.1.1 TRANSMIT QUEUE INTERRUPTS
C1TXQCONL contains the interrupt enable flags and C1TXQSTA contains the interrupt flags for
the TXQ.
The TXQ interrupt occurs when there is a change in the status of the TXQ. There are two
interrupt sources:
• TXQ Not Full Interrupt Flag (TXQNIF)
• TXQ Empty Interrupt Flag (TXQEIF)
Both interrupts can be enabled individually. The interrupts cannot be cleared by the application;
they will be cleared when the condition of the FIFO terminates.
Both interrupt sources are OR’d together and reflected in the TFIF0 flag (C1TXIFL<0>).
12.1.2 RECEIVE FIFO INTERRUPTS – RFIF
The receive FIFO interrupts occur when there is a change in the status of the receive FIFO.
There are three interrupt sources:
• Receive FIFO Full Interrupt Flag (RFFIF)
• Receive FIFO Half Full Interrupt Flag (RFHIF)
• Receive FIFO Not Empty Interrupt Flag (RFNIF)
All three interrupts can be enabled individually. The interrupts cannot be cleared by the
application; they will be cleared when the condition of the FIFO terminates.
The three interrupt sources are OR’d together and reflected in the RFIF<31:16> (C1RXIFH<15:0>)
and RFIF<15:1> (C1RXIFL<15:1>) flags.
12.1.3 TRANSMIT FIFO INTERRUPTS – TFIF
The transmit FIFO interrupts occur when there is a change in the status of the transmit FIFO.
There are three interrupt sources:
• Transmit FIFO Not Full Interrupt Flag (TFNIF)
• Transmit FIFO Half Empty Interrupt Flag (TFHIF)
• Transmit FIFO Empty Interrupt Flag (TFEIF)
All three interrupts can be enabled individually. The interrupts cannot be cleared by the
application; they will be cleared when the condition of the FIFO terminates.
The three interrupt sources are OR’d together and reflected in the C1TXIFL<15:1> and
C1TXIFH<15:0> flags.
12.1.4 RECEIVE FIFO OVERRUN INTERRUPT – RXOVIF
When a message is successfully received, but the FIFO is full, the RXOVIF of the individual
FIFO is set. The flag must be cleared by the application.
12.1.5 TRANSMIT FIFO ATTEMPT INTERRUPT – TXATIF
When the retransmission of a message fails due to an error, and all retransmission attempts are
exhausted, the TXATIF flag is set. The flag must be cleared by the application.

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English