2018 Microchip Technology Inc. DS70005340A-page 107
CAN FD Protocol Module
12.1.6 TRANSMIT EVENT FIFO INTERRUPTS – TEFIF
The TEF interrupts occur when there is a change in the status of the TEF. There are four
interrupt sources:
• TEF Full Interrupt Flag (TEFFIF)
• TEF Half Full Interrupt Flag (TEFHIF)
• TEF Not Empty Interrupt Flag (TEFNEIF)
• TEF Overrun Interrupt Flag (TEFOVIF)
The TEF interrupts work similarly to the receive FIFO interrupts. All four interrupts can be
enabled individually.
TEFFIF, TEFHIF and TEFNEIF cannot be cleared by the application; they will be cleared when
the status of the FIFO terminates.
The TEFOVIF must be cleared by the application.
The four interrupt sources are OR’d together and reflected in the TEFIF flag (C1INTL<4>).
12.2 FIFO Combined Interrupts
The following interrupts are individual FIFO interrupts:
• FIFOs/TXQ: RFIFx, TFIFx, RFOVIFx and TFATIFx
They are combined into single Interrupt Status registers:
• C1RXIFH/L, C1TXIFH/L, C1RXOVIFH/L and C1TXATIFH/L.
The bits in the status registers are mapped to the FIFOs as follows: Bit 0 to TXQ, Bit 1 to
FIFO 1, Bit 2 to FIFO 2, up to Bit 31 to FIFO 31. Since Bit 0 corresponds to the TXQ, Bit 0 of
C1RXIFL and C1RXOVIFL is reserved. Hence, by reading one register, the application can
check the status of all FIFOs for a particular interrupt (e.g., any RFIFx pending).
The FIFO interrupts are enabled in C1FIFOCONxL.
TXQ interrupts are enabled in C1TXQCONL.
Clearing of the FIFO interrupts is explained in Section 12.1 “FIFO Individual Interrupts”.
12.3 Main Interrupts
The C1INT register contains all the main interrupts. The following interrupts are a logical ‘OR’ of
all combined FIFO interrupts: RXIF, TXIF, RXOVIF and TXATIF. These flags are read-only and
must be cleared in preceding hierarchies.
The TEFIF is generated in the TEF. This flag is read-only and must be cleared in preceding
hierarchies.
All interrupts in C1INTH/L can be enabled individually.
12.3.1 INVALID MESSAGE INTERRUPT – IVMIF
If a CAN bus error or DLC mismatch is detected during the last message transmitted or
received, the IVMIF bit will be set. The C1BDIAG1H register sets a flag for each error. The flag
must be cleared by the application.
The following CAN bus errors will trigger the interrupt in case an error frame is transmitted:
CRC, stuff bit, form, bit or ACK.
The flag will not be set if the ESI of a received message is set.
12.3.2 WAKE-UP INTERRUPT – WAKIF
This bit is set if bus activity has been detected while the module is in Sleep mode. The flag must
be cleared by the application.
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