dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 108 2018 Microchip Technology Inc.
12.3.3 CAN BUS ERROR INTERRUPT – CERRIF
The C1TRECH/L registers will count the errors during transmit and receive according to the
ISO11898-1:2015. The CERRIF flag will be set based on the error counter values. The flag
must be cleared by the application.
CERRIF will be set each time a threshold in the TEC/REC counter is crossed by the following
conditions:
• TEC or REC exceeds the error warning state threshold
• The transmitter or receiver transitions to the error passive state
• The transmitter transitions to the bus off state
• The transmitter or receiver transitions from the error passive to error active state
• The module transitions from the bus off to error active state after the bus off recovery
sequence
When the user clears CERRIF, it will remain clear until a new counter crossing occurs.
12.3.4 CAN MODE CHANGE INTERRUPT – MODIF
When the OPMOD<2:0> bits change, the MODIF flag will be set. The flag must be cleared by
the application.
12.3.5 CAN TIMER INTERRUPT – TBCIF
When the Time Base Counter rolls over, TBCIF will be set. The flag must be cleared by the
application.
12.3.6 SYSTEM ERROR INTERRUPT – SERRIF
• Bus Bandwidth Error:
Bandwidth errors can happen during receive and transmit.
Receive Message Assembly Buffer (RX MAB) overflow occurs when the module is unable
to write a received CAN message to RAM before the next message arrives.
Transmit Message Assembly Buffer (TX MAB) underflow occurs when the module cannot
feed the TX MAB fast enough to provide consistent data to the Bit Stream Processor.
The SERRIF flag will be set and the ICODE<6:0> bits (C1VECL<6:0>) will be set
to 100 0101.
• Handling of RX MAB Overflow Errors:
RX MAB overflows are not acceptable for some applications. To prevent overflows, frame
filtering and data saving starts as early as possible; the latest at the beginning of the CRC
field of the received message. Updating the FIFO status has to wait until the beginning of
the 7th bit of the EOF field, since the received frame is only valid at this point. The complete
message has to be saved and the FIFO has to be updated until the end of the arbitration
field of the next message.
In case of an RX MAB overflow, the new message that caused the overflow will be dis-
carded. The module continues to store the message that is completely received and filtered.
Afterwards, the module will be able to receive new messages on the bus. The application
will be notified using the SERRIF bit.
The SERRIF bit (C1INTL<12>) will be cleared by writing a zero to the bit. This will also clear
the SERRIF condition from the ICODEx bits.
• Handling of TX MAB Underflow Errors:
ISO11898-1:2015 requires MAC data consistency: a transmitted message must contain con-
sistent data. If data errors occur due to ECC errors, or TX MAB underflow, the transmission
will not start. If the transmission is in progress, it will stop and the module will transition to
either Restricted Operation or Listen Only mode, which is selectable using the SERRLOM
bit (C1CONH<2>).
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