2018 Microchip Technology Inc. DS70005340A-page 109
CAN FD Protocol Module
The module handles these errors by stopping the transmission and transitioning to Restricted
Operation or Listen Only mode. The CxTX pin will be forced high. Additionally, all TXREQs will
be ignored. The application will be notified using SERRIF. The module will continue to receive
messages.
12.4 Interrupt Handling
The CAN FD Protocol Module allows the application to handle interrupts efficiently by:
• Implementing a lookup table using the C1VECH/L registers.
• Using the status registers and deciding which interrupt to service first.
The application can also use a combination of these two methods to handle interrupts.
12.4.1 INTERRUPT LOOKUP TABLE
The ICODEx and FILHITx bits in the C1VECL register enable the application to use a lookup
table to implement the Interrupt Service Routine (ISR).
The following bit fields allow the application to make full use of the three interrupt pins:
• TXCODE<6:0> bits: Reflect which object has a transmit interrupt pending
• RXCODE<6:0> bits: Reflect which object has a receive interrupt pending
A separate lookup table can be implemented for transmit and receive interrupts.
If more than one object has a pending interrupt, the interrupt or FIFO with the highest number
will show up in RXCODEx, TXCODEx and ICODEx. Once the interrupt with the highest priority
is cleared, the next highest priority interrupt will show up in C1VECH/L. RXCODEx, TXCODEx
and ICODEx are implemented with combinatorial logic using the interrupt flags as inputs.
12.4.2 INTERRUPT STATUS REGISTERS
The CAN FD Protocol Module contains 31 FIFOs and a TXQ. It would be complex to use the
ICODEx bits since the interrupt priorities are determined by the module. Therefore, the following
measures are taken to ensure efficient servicing of interrupts:
• C1INTL and C1INTH contain all main interrupt sources. The application can identify the
categories of interrupts that are pending and decide the order in which interrupts are to be
serviced (e.g., RXIF).
• All categories of interrupts for all FIFOs are combined into individual registers: C1RXIFH/L,
C1TXIFH/L, C1RXOVIFH/L and C1TXATIFH/L. The application can identify the RFIFx bits
that are pending by reading only one register. The same is true for TFIFx, RXOVIF and
TXATIF.
• In the register map, the Interrupt Status registers are arranged in a single block: C1VECH/L,
followed by C1INTH/L, C1RXIFH/L, C1TXIFH/L, C1RXOVIFH/L and C1TXATIFH/L. This
arrangement allows all status registers to be read with a single read access.
Note: There are two types of addressing errors and both of them will cause a soft trap error
on a dsPIC33CH device by setting the CAN bit in the INTCON3 register.
The first addressing error occurs when a FIFO is configured with an invalid address.
This error most commonly occurs when the FIFO points to an unimplemented
address.
The second addressing error commonly occurs when the message destination is
illegal; for example, attempting to write a received message to a program Flash,
which is not directly writable.
To Next Page
Loading...
Need help?
General
