2018 Microchip Technology Inc. DS70005340A-page 31
CAN FD Protocol Module
Register 3-31: C1TXQSTA: CAN Transmit Queue Status Register
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — —TXQCI4
(1)
TXQCI3
(1)
TXQCI2
(1)
TXQCI1
(1)
TXQCI0
(1)
bit 15 bit 8
R-0 R-0 R-0 HS/C-0 U-0 R-1 U-0 R-1
TXABT
(2)
TXLARB
(2)
TXERR
(2)
TXATIF — TXQEIF —TXQNIF
bit 7 bit 0
Legend: HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 TXQCI<4:0>: Transmit Queue Message Index bits
(1)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
bit 7 TXABT: Message Aborted Status bit
(2)
1 = Message was aborted
0 = Message completed successfully
bit 6 TXLARB: Message Lost Arbitration Status bit
(2)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 5 TXERR: Error Detected During Transmission bit
(2)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 Unimplemented: Read as ‘0’
bit 2 TXQEIF: Transmit Queue Empty Interrupt Flag bit
1 = TXQ is empty
0 = TXQ is not empty, at least 1 message is queued to be transmitted
bit 1 Unimplemented: Read as ‘0’
bit 0 TXQNIF: Transmit Queue Not Full Interrupt Flag bit
1 = TXQ is not full
0 = TXQ is full
Note 1: The TXQCI<4:0> bits give a zero-indexed value to the message in the TXQ. If the TXQ is 4 messages
deep (FSIZE = 3), TXQCIx will take on a value of 0 to 3, depending on the state of the TXQ.
2: These bits are updated when a message completes (or aborts) or when the TXQ is reset.
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