dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 30 2018 Microchip Technology Inc.
Register 3-30: C1TXQCONL: CAN Transmit Queue Control Register Low
U-0 U-0 U-0 U-0 U-0 S/HC-1 R/W/HC-0 S/HC-0
— — — — — FRESET TXREQ UINC
bit 15 bit 8
R-1 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0
TXEN
(1)
— —TXATIE— TXQEIE —TXQNIE
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 FRESET: FIFO Reset bit
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset; user should poll
whether this bit is clear before taking any action
0 = No effect
bit 9 TXREQ: Message Send Request bit
1 = Requests sending a message; the bit will automatically clear when all the messages queued in
the TXQ are successfully sent
0 = Clearing the bit to ‘0’ while set (‘1’) will request a message abort
bit 8 UINC: Increment Head/Tail bit
When this bit is set, the FIFO head will increment by a single message.
bit 7 TXEN: TX Enable
(1)
1 = Transmit Message Queue. This bit always reads as ‘1’.
bit 6-5 Unimplemented: Read as ‘0’
bit 4 TXATIE: Transmit Attempts Exhausted Interrupt Enable bit
1 = Enables interrupt
0 = Disables interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 TXQEIE: Transmit Queue Empty Interrupt Enable bit
1 = Interrupt is enabled for TXQ empty
0 = Interrupt is disabled for TXQ empty
bit 1 Unimplemented: Read as ‘0’
bit 0 TXQNIE: Transmit Queue Not Full Interrupt Enable bit
1 = Interrupt is enabled for TXQ not full
0 = Interrupt is disabled for TXQ not full
Note 1: Please refer to the specific device data sheet for the Reset value of the TXEN bit.
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