dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 26 2018 Microchip Technology Inc.
Register 3-23: C1TXATIFH: CAN Transmit Attempt Interrupt Status Register High
(1)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF<31:24>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TFATIF<31:16>: Transmit FIFO/TXQ Attempt Interrupt Pending bits
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: C1TXATIFH: FIFO: TFATIFx (flag needs to be cleared in the FIFO register).
Register 3-24: C1TXATIFL: CAN Transmit Attempt Interrupt Status Register Low
(1)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF<7:0>
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TFATIF<15:0>: Transmit FIFO/TXQ Attempt Interrupt Pending bits
(2)
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: C1TXATIFL: FIFO: TFATIFx (flag needs to be cleared in the FIFO register).
2: TFATIF0 is for the TXQ.