2018 Microchip Technology Inc. DS70005340A-page 19
CAN FD Protocol Module
Register 3-13: C1VECH: CAN Interrupt Code Register High
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— RXCODE<6:0>
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— TXCODE<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 RXCODE<6:0>: Receive Interrupt Flag Code bits
1000001-1111111 = Reserved
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (RFIF<31> is set)
...
0000010 = FIFO 2 interrupt (RFIF<2> is set)
0000001 = FIFO 1 interrupt (RFIF<1> is set)
0000000 = Reserved; FIFO 0 cannot receive
bit 7 Unimplemented: Read as ‘0’
bit 6-0 TXCODE<6:0>: Transmit Interrupt Flag Code bits
1000001-1111111 = Reserved
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (TFIF<31> is set)
...
0000001 = FIFO 1 interrupt (TFIF<1> is set)
0000000 = FIFO 0 interrupt (TFIF<0> is set)
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