2018 Microchip Technology Inc. DS70005340A-page 45
CAN FD Protocol Module
Register 3-48: C1BDIAG1H: CAN Bus Diagnostics Register 1 High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
DLCMM ESI DCRCERR DSTUFERR DFORMERR
— DBIT1ERR DBIT0ERR
bit 15 bit 8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXBOERR
— NCRCERR NSTUFERR NFORMERR NACKERR NBIT1ERR NBIT0ERR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 DLCMM: DLC Mismatch bit
During a transmission or reception, the specified DLC is larger than the PLSIZEx of the FIFO element.
bit 14 ESI: ESI Flag of Received CAN FD Message Set bit
bit 13 DCRCERR: Same as for Nominal Bit Rate
bit 12 DSTUFERR: Same as for Nominal Bit Rate
bit 11 DFORMERR: Same as for Nominal Bit Rate
bit 10 Unimplemented: Read as ‘0’
bit 9 DBIT1ERR: Same as for Nominal Bit Rate
bit 8 DBIT0ERR: Same as for Nominal Bit Rate
bit 7 TXBOERR: Device Went to Bus Off bit (and auto-recovered)
bit 6 Unimplemented: Read as ‘0’
bit 5 NCRCERR: Received Message with CRC Incorrect Checksum bit
The CRC checksum of a received message was incorrect. The CRC of an incoming message does not
match with the CRC calculated from the received data.
bit 4 NSTUFERR: Received Message with Illegal Sequence bit
More than 5 equal bits in a sequence have occurred in a part of a received message where this is not
allowed.
bit 3 NFORMERR: Received Frame Fixed Format bit
A fixed format part of a received frame has the wrong format.
bit 2 NACKERR: Transmitted Message Not Acknowledged bit
Transmitted message was not Acknowledged.
bit 1 NBIT1ERR: Transmitted Message Recessive Level bit
During the transmission of a message (with the exception of the arbitration field), the device wanted to
send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant.
bit 0 NBIT0ERR: Transmitted Message Dominant Level bit
During the transmission of a message (or Acknowledge bit, or active error flag or overload flag), the
device wanted to send a dominant level (data or identifier bit of logical value ‘0’), but the monitored bus
value was recessive. During bus off recovery, this status is set each time a sequence of 11 recessive
bits has been monitored. This enables the CPU to monitor the proceeding of the bus off recovery
sequence (indicating the bus is not stuck at dominant or continuously disturbed).
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