Microchip Technology dsPIC33 series User Manual

 2018 Microchip Technology Inc. DS70005340A-page 35
CAN FD Protocol Module
Register 3-34: C1FIFOSTAx: CAN FIFO Status Register x (x = 1 to 31)
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FIFOCI4
(1)
FIFOCI3
(1)
FIFOCI2
(1)
FIFOCI1
(1)
FIFOCI0
(1)
bit 15 bit 8
R-0 R-0 R-0 HS/C-0 HS/C-0 R-0 R-0 R-0
TXABT
(3)
TXLARB
(2)
TXERR
(2)
TXATIF RXOVIF TFERFFIF TFHRFHIF TFNRFNIF
bit 7 bit 0
Legend: HS = Hardware Settable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 FIFOCI<4:0>: FIFO Message Index bits
(1)
TXEN = 1 (FIFO configured as a transmit buffer):
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN =
0 (FIFO configured as a receive buffer):
A read of this register will return an index to the message that the FIFO will use to save the next
message.
bit 7 TXABT: Message Aborted Status bit
(3)
1 = Message was aborted
0 = Message completed successfully
bit 6 TXLARB: Message Lost Arbitration Status bit
(2)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 5 TXERR: Error Detected During Transmission bit
(2)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit
TXEN =
1 (FIFO configured as a transmit buffer):
1 = Interrupt is pending
0 = Interrupt is not pending
TXEN =
0 (FIFO configured as a receive buffer):
Unused, reads as ‘0’.
bit 3 RXOVIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit buffer):
Unused, reads as ‘0’.
TXEN = 0 (FIFO configured as a receive buffer):
1 = Overflow event has occurred
0 = No overflow event occurred
Note 1: FIFOCI<4:0> gives a zero-indexed value to the message in the FIFO. If the FIFO is 4 messages deep
(FSIZE = 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO.
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the TXQ is reset.

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English