Microchip Technology dsPIC33 series User Manual

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 36  2018 Microchip Technology Inc.
bit 2 TFERFFIF: Transmit/Receive FIFO Empty/Full Interrupt Flag bit
TXEN =
1 (FIFO configured as a transmit FIFO):
Transmit FIFO Empty Interrupt Flag
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message is queued to be transmitted
TXEN =
0 (FIFO configured as a receive FIFO):
Receive FIFO Full Interrupt Flag
1 = FIFO is full
0 = FIFO is not full
bit 1 TFHRFHIF: Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Half Empty Interrupt Flag
1 = FIFO is  half full
0 = FIFO is > half full
TXEN =
0 (FIFO configured as a receive FIFO):
Receive FIFO Half Full Interrupt Flag
1 = FIFO is  half full
0 = FIFO is < half full
bit 0 TFNRFNIF: Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag bit
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Not Full Interrupt Flag
1 = FIFO is not full
0 = FIFO is full
TXEN =
0 (FIFO configured as a receive FIFO):
Receive FIFO Not Empty Interrupt Flag
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
Register 3-34: C1FIFOSTAx: CAN FIFO Status Register x (x = 1 to 31) (Continued)
Note 1: FIFOCI<4:0> gives a zero-indexed value to the message in the FIFO. If the FIFO is 4 messages deep
(FSIZE = 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO.
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the TXQ is reset.

Microchip Technology dsPIC33 series Specifications

General

Brand	Microchip Technology
Model	dsPIC33 series
Category	Motherboard
Language	English