2018 Microchip Technology Inc. DS70005340A-page 69
CAN FD Protocol Module
6.4 Requesting Transmission of Message in Transmit FIFO
After a message is loaded into a transmit FIFO, the message is ready for transmission. The
application initiates the transmission of all messages in a FIFO by setting the TXREQ bit
(C1FIFOCONL<9>) or by setting the corresponding bit in the C1TXREQH/L registers. When all
messages are transmitted, TXREQ gets cleared. The application can request transmission of
multiple FIFOs and the TXQ simultaneously. The FIFO or TXQ with the highest priority will start
transmitting first. Messages in a FIFO will be transmitted First-In-First-Out.
Messages can be loaded into a FIFO while the FIFO is transmitting messages. Since TXREQ is
cleared by the FIFO automatically after the FIFO empties, UINC and TXREQ of the
C1FIFOCONL register must be set at the same time after appending a message. This ensures
that all messages in the FIFO are transmitted, including the appended messages.
6.5 Requesting Transmission of Message in Transmit Queue
After a message is loaded into the TXQ, the message is ready for transmission. The application
initiates the transmission of all messages in the queue by setting TXREQ (C1TXQCONL<9>).
When all messages have been transmitted, TXREQ will be cleared. The application can request
transmission of the TXQ and multiple FIFOs simultaneously. The TXQ or FIFO of the
C1TXQCONL register with the highest priority will start transmitting first. Messages in the TXQ
will be transmitted based on their ID. The message with the highest priority ID and the lowest ID
value will be transmitted first.
Messages can be loaded into the TXQ while the TXQ is transmitting messages. Since TXREQ
is cleared by the TXQ automatically after the TXQ empties, UINC and TXREQ of the
C1TXQCONL register must be set at the same time after appending a message. This ensures
that all messages in the TXQ are transmitted, including the appended messages.
6.6 C1TXREQ Register
The C1TXREQH and C1TXREQL registers contain the TXREQ<31:0> bits of the TXQ and of all
the TX FIFOs. They have the following purposes:
• The user application can request transmission of the TXQ and/or one or more TX FIFOs,
using only one SPI instruction, by setting the corresponding bits in the C1TXREQH/L
registers. Clearing a bit does NOT abort any transmissions.
• Reading the C1TXREQH and C1TXREQL registers gives information about which transmit
FIFOs have transmissions pending.
C1TXREQL<0> is mapped to the TXQ, C1TXREQL<1> is mapped to TX FIFO 1,
C1TXREQL<2> is mapped to TX FIFO 2 and so on. C1TXREQH<31> is mapped to TX FIFO 31.
6.7 Transmit Priority
The transmit priority of the FIFOs and TXQ needs to be configured using the TXPRIx bits
(C1FIFOCONxH<4:0> and C1TXQCONH<4:0>).
Before transmitting a message, the priorities of the TXQ and the TX FIFOs queued for
transmission are compared. The FIFO/TXQ with the highest priority will be transmitted first. For
example, if transmit FIFO 1 has a higher priority setting than FIFO 3, all messages in FIFO 1 will
be transmitted first. If multiple FIFOs have the same priority, the FIFO with the highest index is
transmitted. For example, if FIFO 1 and FIFO 3 have the same priority setting, all messages in
FIFO 3 will be transmitted first. If the TXQ and one or more FIFOs have the same priority, all
messages in the TXQ will be transmitted first.
The transmit priority will be recalculated after every successful transmission of a single
message.
6.7.1 TRANSMIT PRIORITY OF MESSAGES IN FIFO
In this method, the messages in a FIFO are transmitted First-In-First-Out.
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