Midland SYN-TECH 70-050 - Page 10

THEORY OF OPERATION
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PLL/Synthesizer Function
The frequency synthesizer consists of two phase-locked loops. One loop
(Main PLL) is controlled directly by the microcomputer and generates
the receive local oscillator frequency. This loop also generates a
frequency used in the second loop (Transmit PLL) for transmitter
operat ion .
Reference Oscillator and Main PLL
A stable frequency for the entire radio is generated by a crystal
oscillator composed of X101, Q701 and related components. This
oscillator operates at 5.12 MHz and stability is maintained by use of
a posistor crystal heater. This 5.12 MHz signal is divided by 1024 in
IC701 to give the 5kHz reference frequency for the Main PLL loop
consisting of IC701 (phase comparator and programmable divider), Q704-
706 (loop low pass filter), D702/707 (VCO), and IC703 (pre-scaler).
The VCO frequency is equal to the channel frequency plus 10.7 MHz in
receive and channel frequency plus 10.24 Mhz in transmit. The VCO
frequency is divided by 32/33 by pre — scaler IC703 and further divided
in IC701. The division ratio of IC701 is controlled by the 8 bit code
latched into the shift register IC902 from the E/PR0M IC951 under
control of the microcomputer IC901 . The 8 bit code is sent in serial
fashion from IC902 to 1C701 under microcomputer control. Besides being
a programmable divider, IC701 is also a phase comparator which gene¬
rates an error signal for VCO control if the programmable divider
output, is out of phase with the 5 KHz reference frequency.
Modulator and Transmit PLL
The 5.12 MHz oscillator output is also fed to IC702 where it is
divided by 8 to give 640 KHz. This signal goes directly to the trans¬
mit phase shift modulator D101/D102. Audio from the microphone is
shaped and limited by IC101 (instantaneous deviation control),, fil¬
tered and buffered and fed to the phase shift modulator. The modulator
output becomes the reference frequency for the Transmit PLL loop
consisting of IC103 (phase comparator), D104/Q108 (VCO), D108 (mixer),
and 1C106 (fixed divider). The VCO output, is at the transmit channel
frequency and is mixed at D108 with the Ftx + 10.24 MHz signa.. from
the Main PLL loop to yield 10.24 MHz. This frequency is divided by 16
at 1C106 to give 640 KHz and compared with the 640 KHz reference
signal from the modulator. Thus the VCO output is forced to track the
modulated reference signal, reproducing this modulation at the trans¬
mit frequency. 1C102 detects any large differences between the two
phase comparator inputs and generates an out-of-lock signal which
biases Q111 on and prevents any transmitter signal from reaching the
power amplifier stages. Q111 is also biased on during receive by a
signal from the microcomputer IC901 pin 6.
Transmit Power Amplifier and APC (Automatic Power Controller)
The transmit PLL output, is amplified by Q1 10 before being fed : o the
PA section. The (1110 output is amplified to rated output by Q501 (pre¬
driver), Q502 (driver), and the final transistor Q503. A sample of the
RF output is detected by D501 and coupled to the diffential amplifier
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