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Midland SYN-TECH 70-050 - Page 11

Midland SYN-TECH 70-050
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THEORY
OF
OPERATION
70-050/055
Q505/Q506.
The
output
of
Q505
controls
the
conduction
of
Q
5
0
4
which
in
turn
controls
the
gain
of
the
pre-driver
Q501.
Thus
any
changes
in
output
power
are
automatically
corrected
by
this
control
loop.
Output
power
is
set
at
alignment
by
RV502.
Transmitter
harmonics
are
eliminated
by
output
low
pass
filtering
composed
of
L513-L515
and
C521-C527.
Transmit/receive
switching
is
accomplished
by
antenna
relay
K
50
1
.
Receiver
RF/IF/Detector
The
receiver
front
end
consists
of
filtering
by
C20I-C206
ami
L201-
L203
and
RF
amplification
by
Q201.
After
further
filtering
the
RF
signal
is
mixed
at
the
FET
mixer
Q202
with
the
local
oscillator
signal
generated
by
the
Main
PLL
loop
to
give
the
10.7
MHz
IF.
The
IF
signal
is
filtered
by
the
crystal
filter
FL251,
amplified
by
Q251
and
fed
to
the
internal
mixer
of
IC
2
51.
The
2nd
local
oscillator
frequency
of
10.245
MHz
is
generated
by
X251
and
the
IC251
internal
oscillator
and
injected
into
the
internal
mixer,
producing
the
2nd
IF
of
455
KHz.
The
2nd
IF
signal
is
filtered
by
FL252
and
FL253,
amplified
and
limited
by
the
amplifier/limiter
stage
of
IC251,
and
injected
into
the
quadrature
circuit
consisting
of
L252
and
the
internal
balanced
mixer
of
IC251.
The
output
of
the
balanced
mixer
is
the
detected
audio
signal.
Squelch
and
Audio
Amplifier
The
noise
signal
from
the
detector
is
amplified
by
Q252,
detected
by
D253
and
controlled
in
level
by
the
squelch
control
RV301.
This
detected
noise
signal
is
coupled
to
the
DC
switching
amplifier
of
IC251.
Under
conditions
of
no
RF
signal,
the
detected
noise
signal
increases
and
turns
on
the
DC
switching
amplifier,
which
in
turn
biases
off
the
transceiver
audio
squelch
gate
(Q259).
The
detected
audio
signal
is
buffered
by
Q250
and
passed
through
the
squelch
gate
and
volume
control
RV302
to
the
audio
power
amplifier
IC252
and
then
to
the
speaker.
Microcomputer
Channel
Data
Transfer
At
unit
power-up
a
pulse
is
generated
by
Q405,
resetting
the
microcomputer
to
an
auto
test
mode.
A
check
is
made
to
insure
the
E/PR0M
module
is
installed.
If
valid
data
is
present
"at
the
E/PR0M,
3
bits
of
address
data
corresponding
to
the
selected
receive
channel
frequency
are
strobed
from
the
microcomputer
IC901
to
the
latch
IC
IC952.
The
remaining
three
address
bits
are
then
strobed
and
latched
in
IC952.
The
E/PR0M
data
corresponding
to
the
selected
receive
channel
is
then
strobed
to
the
8
bit
shift
register
IC902
.
which
transfers
this
data
serially
to
the
programmable
divider
IC701
under
microcomputer
control.
IC701
divides
its
input
signal
by
the
correct
ratio
to
yield
the
desired
local
oscillator
frequency.
IC701
outputs
an
out-of-lock
signal
which
mutes
the
receiver
until
phase
lock
is
achieved.
The
microcomputer
strobes
data
corresponding
to
the
selected
channel
to
the
latched
LED
display
drivers
IC301
and
IC302
which
in
turn
drive
the
channel
LEDs.
Brightness
of
the
LED
display
is
automatically
adjusted
to
ambient
light
conditions
by
photosensor
CDS301
and
transistors
Q301
and
Q302.
1
1

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