APPENDICES
Appendix 1 Special Relay List
App - 14
9
Parameters
10
Device Explanation
11
CPU Module Processing
Time
12
Procedure for Writing
Program to CPU ModuleAppendicesIndex
*7: The Universal model QCPU except the Q02UCPU.
TableApp.8 Special relay
Number Name Meaning Explanation
Set by
(When Set)
Corres-
ponding
ACPU
M9
Corresponding
CPU
SM796
Block information
using dedicated
instruction of Multiple
CPU high speed
transmission (for CPU
No.1)
OFF : Block is secured
ON : Block set by SD796
cannot be secured
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the dedicated instruction of Multiple CPU high
speed transmission (target CPU = CPU No.1) is less
than the number of blocks specified by SD796.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
S (When
instruction/END
processing
executed)
New QnU
SM797
Block information
using dedicated
instruction of Multiple
CPU high speed
transmission (for CPU
No.2)
OFF : Block is secured
ON : Block set by SD797
cannot be secured
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the dedicated instruction of Multiple CPU high
speed transmission (target CPU = CPU No.2) is less
than the number of blocks specified by SD797.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
S (When
instruction/END
processing
executed)
New QnU
SM798
Block information
using dedicated
instruction of Multiple
CPU high speed
transmission (for CPU
No.3)
OFF : Block is secured
ON : Block set by SD798
cannot be secured
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the dedicated instruction of Multiple CPU high
speed transmission (target CPU = CPU No.3) is less
than the number of blocks specified by SD798.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
S (When
instruction/END
processing
executed)
New QnU
SM799
Block information
using dedicated
instruction of Multiple
CPU high speed
transmission (for CPU
No.4)
OFF : Block is secured
ON : Block set by SD799
cannot be secured
• Turns ON when the number of the remaining blocks
of the dedicated instruction transmission area used
for the dedicated instruction of Multiple CPU high
speed transmission (target CPU = CPU No.4) is less
than the number of blocks specified by SD799.
Turns ON at instruction execution. Turns OFF when
the empty area exists at END processing.
S (When
instruction/END
processing
executed)
New
QnU
*7