Receive Audio Circuits
Theory of Operation 6.3-13
6.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC (U5201-28) on DET AUDIO.
The signal is AC coupled by C0181 and enters the AFIC via the RX IN pin U0103-7.
Inside the AFIC the signal entering RX IN (U0103-7) goes through the audio path while the signal
entering PL DPL IN (U0103-8) via C0182 goes through the PL/DPL path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth
being received, then a LPF filter to remove any frequency components above 3000Hz and then an
HPF to remove any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects
of FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level
is set depending on the value of the volume control. Finally, the filtered audio signal passes through
an output buffer within the AFIC. The audio signal exits the AFIC at RX AUDIO U0103-23.
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum/
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated
from the voice information before processing. Any sub-audible signalling enters the AFIC from the IF
IC at PL DPL IN U0103-8. Once inside it goes through the PL/DPL path. The signal first passes
through one of 2 low pass filters, either PL low pass filter or DPL/LST low pass filter. Either signal is
then filtered and goes through a limiter and exits the AFIC at PL DPL DECODER OUT U0103-27. At
this point the signal will appear as a square wave version of the sub-audible signal which the radio
received. The microprocessor (U0101-64) will decode the signal directly to determine if it is the tone/
code which is currently active on that mode.
6.3 Audio Amplification Speaker (+) Speaker (-)
The output of the AFIC´s digital volume pot, U0103-23 is routed through a voltage divider formed by
R0401 and R0402 to set the correct input level to the audio PA (U0401). This is necessary because
the gain of the audio PA is 46 dB, and the AFIC output is capable of overdriving the PA unless the
maximum volume is limited.
The audio then passes through C0401 which provides AC coupling and low frequency roll-off.
C0402 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the audio
power amplifier U0401.
The audio power amplifier has one inverted and one non-inverted output that produces the
differential audio output SPK+ / SPK- (U0401-4/6). The inputs for each of these amplifiers are pins 1
and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via AUDIO PA ENABLE signal from the AFIC (U0103-40). When the base
of Q0401 is low, the transistor is off and U0401-8 is high, using pull up resistor R0406, and the Audio
PA is ON. The voltage at U0401-8 must be above 8.5VDC to properly enable the device. If the
voltage is between 3.3 and 6.4V, the device will be active but has its input (U0401-1/9) off. R0404
ensures that the base of Q0401 is high on power up. Otherwise there may be an audio pop due to
R0406 pulling U0401-8 high before the software can switch on Q0401.
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