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MSI 785G-E65 Series - Page 60

MSI 785G-E65 Series
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3-22
BIOS Setup
MS-7576
BIOS Setup
MS-7576
Advance DRAM Con󰘰guraton
Press <Enter> to enter the sub-menu and the followng screen appears.
DRAM Tmng Mode
Ths 󰘰eld has the capacty to automatcally detect all of the DRAM tmng. If you set
ths 󰘰eld to [DCT 0], [DCT 1] or [Both], some 󰘰elds wll appear and selectable. DCT
0 controls channel A and DCT1 controls channel B.
CAS Latency (CL)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld s adjust
-
able. Ths controls the CAS latency, whch determnes the tmng delay (n clock
cycles) before SDRAM starts a read command after recevng t.
tRCD
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld s adjust
-
able. When DRAM s refreshed, both rows and columns are addressed separately.
Ths setup tem allows you to determne the tmng of the transton from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld s adjust
-
able. Ths settng controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If nsu󰘲cent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh may be ncomplete and DRAM may fal to retan data.
Ths tem apples only when synchronous DRAM s nstalled n the system.