MSI 880G-E45 Series - Page 43

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DIMM1~4 Memory SPD Information
Press <Enter> to enter the sub-menu. This sub-menu displays the information of
installed memory.
Advance DRAM Con󰘰guration
Press <Enter> to enter the sub-menu.
DRAM Timing Mode
This 󰘰eld has the capacity to automatically detect all of the DRAM timing. If you set
this 󰘰eld to [DCT 0], [DCT 1] or [Both], some 󰘰elds will appear and selectable. DCT
0 controls channel A and DCT1 controls channel B.
CAS Latency (CL)
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. This controls the CAS latency, which determines the timing delay (in clock
cycles) before SDRAM starts a read command after receiving it.
tRCD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. This setting controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If insu󰘲cient time is allowed for the RAS to accumulate its
charge before DRAM refresh may be incomplete and DRAM may fail to retain data.
This item applies only when synchronous DRAM is installed in the system.
tRAS
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. This setting determines the time RAS takes to read from and write to a memory
cell.
tRTP
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. This setting controls the time interval between a read and a precharge com-
mand.
tRC
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. The row cycle time determines the minimum number of clock cycles a memory
row takes to complete a full cycle, from row activation up to the precharging of the
active row.
tWR
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. It speci󰘰es the amount of delay (in clock cycles) that must elapse after the
completion of a valid write operation, before an active bank can be precharged. This
delay is required to guarantee that data in the write bu󰘯ers can be written to the
memory cells before precharge occurs.
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