MSI 880G-E45 Series - Page 44

En-34
MS-7576 Mainboard
tRRD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. Speci󰘰es the active-to-active delay of di󰘯erent banks.
tWTR
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], the 󰘰eld is adjust-
able. This item controls the Write Data In to Read Command Delay memory timing.
This constitutes the minimum number of clock cycles that must occur between the
last valid write operation and the next read command to the same internal bank of
the DDR device.
tRFC0~3
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these 󰘰elds are
adjustable. These settings determine the time RFC take to read from and write to
memory cells.
tWRTTO
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these 󰘰elds
are adjustable. Timing of Read to Write turnaround for data; the minimum cycle
time between command last clock of CAS read operation to next command write
operation. If you set this item smaller, system will run faster but might be more
unstable. Please set it depends on memory module.
tWRRD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these 󰘰elds are
adjustable. Timing of Write to Read; the minimum cycle time from last clock of 󰘰rst
virtual CAS write-burst operation to a following one read-burst operation for di󰘯erent
chip or DIMM.If you set this item smaller, system will run faster but might be more
unstable.Please set it depends on memory module.
tWRWR
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these 󰘰elds are
adjustable. Timing of Write to Write; the minimum cycle time from last clock of 󰘰rst
virtual CAS write-burst operation to a following write-burst peration that changed the
enabled terminator.If you set this item smaller, system will run faster but might be
more unstable. Please set it depends on memory module.
tRDRD
When the DRAM Timing Mode sets to [DCT 0], [DCT1] or [Both], these 󰘰elds are
adjustable. Timing of Read to Read; the minimum cycle time from last clock of a 󰘰rst
virtual CAS read-burst operation to a following one read-burst operation for di󰘯erent
chip or DIMM. If you set this itemsmaller, system will run faster but might be more
unstable.Please set it depends on memory module.
DRAM Drive Strength
This feature allows you to control the memory data bus' signal strength. Increasing
the drive strength of the memory bus can increase stability during overclocking.
DRAM Advance Control
This 󰘰eld has the capacity to automatically detect the advanced DRAM timing. If
you set this 󰘰eld to [DCT 0], [DCT 1] or [Both], some 󰘰elds will appear and
selectable.
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