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BIOS Setup
DRAM Timing
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to By SPD enables
DRAM timings to be determined by BIOS based on the configurations
on the SPD. Selecting Manual allows users to configure the DRAM
timings manually.
DRAM CAS Latency
This controls the timing delay (in clock cycles) before SDRAM starts a
read command after receiving it. Settings: 2, 2.5. 2 (clocks) increases
the system performance the most while 2.5 (clocks) provides the most
stable performance.
Bank Interleave
This field enables or disables bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed. Settings: Disabled,
4 Bank, 2 Bank.
Precharge to Active (Trp)
This item allows you to control the number of DRAM clocks used for
DRAM parameter Trp. Trp specifies the minimum clock cycles required
for the precharge command to be transferred to the active command.
Setting options: 2T, 3T.
Active to Precharge (Tras)
This item allows you to control the number of DRAM clocks used for
DRAM parameters Tras. Tras specifies the minimum clock cycles
required for the active command to be transferred to the precharge
command. Setting options: 5T, 6T.
Active to CMD (Trcd)
This item allows you to control the number of DRAM clocks used for
DRAM parameters Trcd. Trcd specifies the minimum clock cycles
required for the active command to be transferred to the re-active
command. Setting options: 2T, 3T.
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