PIN ASSIGNMENT
Top View
1
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9
10
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12
13
14
15
16
17
18
19
20
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22
23
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25
26
27
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
A
13
A12
A10/AP
A
0
A1
A2
A3
VDD
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A9
A8
A7
A6
A5
A4
VSS
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11 Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
A12 , A13 Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS , WE active.
L(U)DQM Data Input / Output Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC No Connection This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
cigoL lortnoC
Column
Address
Buffer
&
Refresh
Counter
Row
ddress
Buffer
&
Refresh
Counter
Bank D
redoceD woR
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
tiucriC hctaL
tuptuO & tupnI
reffuB
ddress
Clock
Generator
CLK
CKE
redoceD dnammoC
CS
RAS
CAS
WE
2-23
64M SDRAM (M12L64164A) : IC12
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