Appendix B Timing Diagrams
© National Instruments Corporation B-39 M Series User Manual
Gate Pulse Width
Figure B-47 and Table B-31 show the timing requirements for Counter n
Gate. The requirements depend on the gating mode.
Figure B-47. Counter n Gate Pulse Width Timing Diagram
Gate to Source Setup and Hold
The counter can be modeled as a set of flip flops where the D input is Count
Enable and the clock input is Selected Source, as shown in Figure B-41.
This section shows the setup and hold requirements for two different cases:
• A PFI pin drives Counter n Source and a different PFI pin drives
Counter n Gate
• The general case (all other combinations of signals driving Source and
Gate)
Figure B-48 and Table B-32 show the setup and hold requirements at the
PFI pins for the first case (where a PFI pin drives Counter n Source and a
different PFI pin drives Counter n Gate).
Figure B-48. Gate to Source Setup and Hold Timing Diagram
Table B-31. Counter n Gate Pulse Width Timing
Time Description Gating Mode Min (ns)
*
Max (ns)
t
7
Counter n Gate Pulse Width Edge 12.0 —
Counter n Gate Pulse Width Level One Source Period —
*
The times in this table are measured at the pin of the M Series device. That is, t
7
specifies the minimum pulse width of a
signal driving a PFI, RTSI, or PXI_STAR pin when that signal is internally routed to Counter n Gate.
Counter
n
Gate
t
7
t
7
t
8S
t
8H
PFI (Gate)
PFI (Source)
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