National Instruments NI 6225 - Page 368

Appendix B Timing Diagrams
© National Instruments Corporation B-45 M Series User Manual
Table B-37 shows delays for generating different clocks using an External
Reference Clock and the PLL.
Figure B-53. Generating Different Clocks Using an External Reference Clock
and the PLL
Table B-36. Generating Different Clocks from the Onboard 80 MHz Oscillator
Time From To Min (ns) Max (ns)
t
1
Onboard 80 MHz Oscillator 80 MHz Timebase 4.0 9.0
t
2
80 MHz Timebase 20 MHz Timebase 0.5 2.5
t
3
80 MHz Timebase 100 kHz Timebase 1.0 5.0
Table B-37. Generating Different Clocks Using an External Reference Clock and the PLL
Time From To Min (ns) Max (ns)
t
4
80 MHz Timebase 20 MHz Timebase 1.5 5.0
t
5
The source of the external
reference clock (RTSI <0..7>,
STAR_TRIG, PXI_CLK10)
80 MHz Timebase
(through PLL_OUT)
1.0 5.5
RTSI <0..7>
STAR_TRIG
PXI_CLK10
(Reference Clock)
80 MHz Timebase (PLL)
20 MHz Timebase (PLL)
t
4
t
5