Chapter 3 Register Map and Descriptions
©
National Instruments Corporation 3-23 PCI E Series RLPM
G0 G1 Select Register
The G0 G1 Select Register contains 8 bits that control the logical DMA selection for the two
general purpose counter timer resources. The contents of this register are cleared upon power
up and after a reset condition.
Address: Base address + 0B (hex)
Type: Write-only
Word Size: 8-bit
Bit Map:
Bit Name Description
7–4 GPCT1 <D..A> General Purpose Counter Timer 1 Logical Channel C
through A—These four bits select the MITE logical
channels that the GPCT1 uses. You can only set one of
these bits at a time.
3–0 GPCT0 <D..A> General Purpose Counter Timer 0 Logical Channel C
through A—These four bits select the MITE logical
channels that the GPCT1 uses. You can only set one of
these bits at a time.
7 6 5 4 3 2 1 0
GPCT1 D GPCT1 C GPCT1 B GPCT1 A GPCT0 D GPCT0 C GPCT0 B GPCT0 A
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