NI Digital System Development Board User Manual | © National Instruments | 3
Features
Figure 1. The Digital System Development Board
The DSDB includes the following features:
ZYNQ XC7Z020-1CLG484C
• 650 Mhz dual-core Cortex-A9 processor
• DDR3 memory controller with 8 DMA channels
• High-bandwidth peripheral controllers: 1G Ethernet, SDIO
• Low-bandwidth peripheral controller: SPI, UART, CAN, I2C
• On-chip analog-to-digital converter (XADC) Programmed using JTAG, Quad-SPI Flash, or
microSD
•
Reprogrammable logic equivalent to Artix-7 FPGA
• 13,300 logic slices, each with four 6-input LUTs and eight flip-flops
• 560 KB of fast block RAM
• Four clock management tiles, each with a phase-locked loop (PLL) and mixed-mode
clock manager (MMCM)
• 220 DSP slices
• Internal clock speeds exceeding 450 MHz
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