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N32G031 series

32-bit ARM Cortex

-M0 microcontroller

User manual V2.0

Main Page

Table of Contents2
Abbreviations in the Text27
List of Abbreviations for Registers27
Available Peripherals27
Memory and Bus Architecture28
System Architecture28
Bus Architecture28
Figure 2-1 Bus Architecture29
Bus Address Mapping30
Figure 2-2 Bus Address Map30
Table 2-1 List of Peripheral Register Addresses31
Boot Management32
Embedded Boot Loader33
Memory System33
FLASH Specification33
Table 2-2 List of Boot Mode33
Table 2-3 Flash Bus Address List34
Option Byte37
Table 2-4 Option Byte List38
Write Protect39
Table 2-5 Read Protection Configuration List39
Table 2-6 Flash Read-Write-Erase41
Sram45
FLASH Register Description46
Table 2-7 FLASH Register Overview46
Power Control (PWR)53
General Description53
Power Supply53
Power Supply Supervisor54
Figure 3-1 Power Supply Block Diagram54
Figure 3-2 Power on Reset/Power down Reset Waveform55
Programmable Voltage Detector (PVD)55
Nrst56
Power Modes56
Table 3-1 Power Modes56
Figure 3-3 PVD Threshold Diagram56
Table 3-2 Peripheral Running Status57
LPRUN Mode58
SLEEP Mode59
Enter SLEEP Mode59
Exit SLEEP Mode59
STOP Mode59
PD Mode60
Debug Support61
Low Power Mode Debug Support61
Peripheral Debug Support61
PWR Registers61
PWR Register Overview61
Table 3-3 PWR Register Overview61
Power Control Register (PWR_CTRL)62
Power Control Status Register (PWR_CTRLSTS)63
Power Control Register 2 (PWR_CTRL2)65
Power Control Register 3 (PWR_CTRL3)65
Power Control Register 4 (PWR_CTRL4)65
Power Control Register 5 (PWR_CTRL5)66
Power Control Register 6 (PWR_CTRL6)67
Debug Control Register (DBG_CTRL)67
Reset and Clock Control (RCC)70
Reset Control Unit70
Power Reset70
System Reset70
Software Reset71
Low-Power Management Reset71
Clock Control Unit72
Figure 4-1 System Reset Generation72
Clock Tree Diagram74
Figure 4-2 Clock Tree74
HSE Clock75
Figure 4-3 HSE Clock Source75
External Crystal/Ceramic Resonator (HSE Crystal)75
HSI Clock76
PLL Clock76
LSE Clock77
LSI Clock77
Figure 4-4 PLL Clock Configuration77
System Clock (SYSCLK) Selection78
Clock Security System (CLKSS)78
RTC Clock78
Watchdog Clock78
LPUART Clock78
LPTIME Clock79
Clock Output(MCO)79
RCC Registers79
RCC Register Overview79
Table 4-1 RCC Register Overview79
Clock Control Register (RCC_CTRL)81
Clock Configuration Register (RCC_CFG)82
Clock Interrupt Register (RCC_CLKINT)85
APB2 Peripheral Reset Register (RCC_APB2PRST)88
APB1 Peripheral Reset Register (RCC_APB1PRST)89
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)90
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)92
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)93
Low Speed Clock Control Register (RCC_LSCTRL)95
Control/Status Register (RCC_CTRLSTS)96
AHB Peripheral Reset Register (RCC_AHBPRST)98
Clock Configuration Register 2(RCC_CFG2)99
Table 5-25 ADC100
EMC Control Register 3 (RCC_EMCCTRL)101
GPIO and AFIO104
Summary104
Function Description105
I/O Mode Configuration105
Table 5-1 I/O Port Configuration Table105
Figure 5-1 Basic Structure of I/O Ports105
Table 5-2 I/O List of Functional Features of the Pin106
Figure 5-2 Input Floating / Pull-Up / Pull-Down Configuration Mode107
Figure 5-3 Output Mode108
Figure 5-4 Alternate Function Mode109
Figure 5-5 Analog Function Mode with High Impedance109
Status after Reset110
Individual Bit Setting and Bit Clearing110
External Interrupt /Wakeup Line110
Alternate Function110
Table 5-3 I/O List of Functional Features of the Pin111
Table 5-4 TIM1 Alternate Function I/O Remapping111
Table 5-5 TIM8 Alternate Function I/O Remapping112
Table 5-6 TIM3 Alternate Function I/O Remapping112
Table 5-7 LPTIM Alternate Function I/O Remapping113
Table 5-8 USART1 Alternate Function I/O Remapping113
Table 5-9 USART2 Alternate Function I/O Remapping114
Table 5-10 LPUART Alternate Function I/O Remapping114
Table 5-11 I2C1 Alternate Function I/O Remapping115
Table 5-12 I2C2 Alternate Function I/O Remapping115
Table 5-13 SPI1/I2S Alternate Function I/O Remapping116
Table 5-14 SPI2 Alternate Function I/O Remapping117
Table 5-15 COMP Alternate Function I/O Remapping117
Table 5-16 BEEPER Alternate Function I/O Remapping117
Table 5-17 EVENTOUT Alternate Function I/O Remapping117
Table 5-18 RTC Alternate Function I/O Remapping118
Table 5-19 RCC Alternate Function I/O Remapping118
Table 5-20 OSC_IN/OSC_OUT Alternate Function I/O Remapping118
Table 5-21 OSC32 Alternate Function Remapping119
Table 5-22 OSC Alternate Function Remapping119
Table 5-23 ADC External Trigger Injection Conversion Alternate Function Remapping119
I/O Configuration of Peripherals120
Table 5-24 ADC External Trigger Regular Conversion Alternate Function Remapping120
Table 5-26 PVD120
Table 5-27 TIM1/TIM8120
Table 5-28 TIM3 and LPTIM120
Table 5-29 USART120
Table 5-30 LPUART121
Table 5-31 I2C121
Table 5-32 SPI121
Table 5-33 COMP121
GPIO Locking Mechanism122
Table 5-34 BEEPER122
Table 5-35 Other122
GPIO Registers123
GPIO Register Overview123
Table 5-36 GPIO Register Overview123
GPIO Port Mode Description Register (Gpiox_Pmode)124
GPIO Port Type Definition (Gpiox_Potype)125
GPIO Slew Rate Configuration Register (Gpiox_Sr)125
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupd)126
GPIO Port Input Data Register (Gpiox_Pid)127
GPIO Port Output Data Register (Gpiox_Pod)127
GPIO Port Bit Set/Clear Register (Gpiox_Pbsc)128
GPIO Port Configuration Lock Register (Gpiox_ PLOCK)129
GPIO Alternate Function Low Register (Gpiox_Afl)129
GPIO Alternate Function High Register (Gpiox_Afh)130
GPIO Port Bit Clear Register (Gpiox_Pbc)131
GPIO Driver Strength Configuration Register (Gpiox_ DS)132
AFIO Registers132
AFIO Register Overview132
Table 5-37 AFIO Register Overview132
AFIO Configuration Register (AFIO_CFG)133
AFIO External Interrupt Configuration Register 1 (AFIO_EXTI_CFG1)134
AFIO External Interrupt Configuration Register 2 (AFIO_EXTI_CFG2)134
AFIO External Interrupt Configuration Register 3 (AFIO_EXTI_CFG3)135
AFIO External Interrupt Configuration Register 4 (AFIO_EXTI_CFG4)136
Interrupts and Events137
Nested Vectored Interrupt Controller137
Systick Calibration Value Register137
Interrupt and Exception Vectors137
Table 6-1 Vector Table137
External Interrupt/Event Controller (EXTI)140
Introduction140
Main Features140
Functional Description141
Figure 6-1 Extenal Interrupt/Event Controller Block Diagram141
EXTI Line Mapping143
Figure 6-2 External Interrupt Generic I/O Mapping143
EXTI Registers145
EXTI Register Overview145
Interrupt Mask Register(EXTI_IMASK)145
Table 6-2 EXTI Register Overview145
Event Mask Register(EXTI_EMASK)146
Rising Edge Trigger Selection Register(EXTI_RT_CFG)146
Falling Edge Trigger Selection Register(EXTI_FT_CFG)147
Software Interrupt Enable Register(EXTI_SWIE)147
Interrupt Request Pending Register(EXTI_PEND)148
RTC Timestamp Trigger Source Selection Register (EXTI_TS_SEL)149
DMA Controller150
Introduction150
Main Features150
Block Diagram151
Function Description151
DMA Operation151
Figure 7-1 DMA Block Diagram151
Channel Priority and Arbitration152
DMA Channels and Number of Transfers152
Programmable Data Bit Width, Alignment and Endians152
Table 7-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)152
Peripheral/Memory Address Incrementation154
Channel Configuration Procedure154
Flow Control155
Circular Mode155
Table 7-2 Flow Control Table155
Error Management156
Interrupt156
DMA Request Mapping156
Table 7-3 DMA Interrupt Request156
DMA Registers157
DMA Register Overview157
Table 7-4 DMA Request Mapping157
Table 7-5 DMA Register Overview157
DMA Interrupt Status Register (DMA_INTSTS)158
DMA Interrupt Flag Clear Register (DMA_INTCLR)159
DMA Channel X Configuration Register (Dma_Chcfgx)160
DMA Channel X Transfer Number Register (Dma_Txnumx)162
DMA Channel X Peripheral Address Register (Dma_Paddrx)162
DMA Channel X Memory Address Register (Dma_Maddrx)163
DMA Channel X Channel Request Select Register (Dma_Chselx)163
CRC Calculation Unit165
CRC Introduction165
CRC Main Features165
CRC32 Module165
CRC16 Module165
CRC Function Description166
Crc32166
Crc16166
Figure 8-1 CRC Calculation Unit Block Diagram166
CRC Registers167
CRC Register Overview167
CRC32 Data Register (CRC_CRC32DAT)167
CRC32 Independent Data Register (CRC_CRC32IDAT)167
Table 8-1 CRC Register Overview167
CRC32 Control Register (CRC_CRC32CTRL)168
CRC16 Control Register (CRC_CRC16CTRL)168
CRC16 Input Data Register (CRC_CRC16DAT)169
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)169
LRC Result Register (CRC_LRC)170
Advanced-Control Timers (TIM1 and TIM8)171
TIM1 and TIM8 Introduction171
Main Features of TIM1 and TIM8171
TIM1 and TIM8 Function Description172
Time-Base Unit172
Figure 9-1 Block Diagram of TIM1 and TIM8172
Prescaler Description173
Counter Mode173
Figure 9-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4173
Up-Counting Mode173
Figure 9-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N175
Down-Counting Mode177
Figure 9-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N177
Center-Aligned Mode177
Figure 9-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N178
Figure 9-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)179
Counter Underflow179
Repetition Counter179
Figure 9-8 Repeat Count Sequence Diagram in Down-Counting Mode180
Figure 9-9 Repeat Count Sequence Diagram in Up-Counting Mode181
Figure 9-10 Repeat Count Sequence Diagram in Center-Aligned Mode181
Clock Selection182
Figure 9-11 Control Circuit in Normal Mode, Internal Clock Divided by 1182
Figure 9-12 TI2 External Clock Connection Example183
Figure 9-13 Control Circuit in External Clock Mode 1184
Figure 9-14 External Trigger Input Block Diagram184
Capture/Compare Channels185
Figure 9-15 Control Circuit in External Clock Mode 2185
Figure 9-16 Capture/Compare Channel (Example: Channel 1 Input Stage)186
Figure 9-17 Capture/Compare Channel 1 Main Circuit187
Figure 9-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)187
Input Capture Mode188
Figure 9-19 Output Part of Channelx (X= 4)188
PWM Input Mode189
Forced Output Mode190
Figure 9-20 PWM Input Mode Timing190
Output Compare Mode191
PWM Mode192
PWM Center-Aligned Mode192
Figure 9-21 Output Compare Mode, Toggle on OC1192
Figure 9-22 Center-Aligned PWM Waveform (AR=8)193
Figure 9-23 Edge-Aligned PWM Waveform (APR=8)194
One-Pulse Mode195
Figure 9-24 Example of One-Pulse Mode195
Clearing the Ocxref Signal on an External Event196
Complementary Outputs with Dead-Time Insertion197
Figure 9-25 Clearing the Ocxref of Timx197
Figure 9-26 Complementary Output with Dead-Time Insertion198
Break Function199
Debug Mode201
Timx and External Trigger Synchronization201
Slave Mode: Reset Mode201
Figure 9-27 Output Behavior in Response to a Break201
Slave Mode: Trigger Mode202
Figure 9-28 Control Circuit in Reset Mode202
Slave Mode: Gated Mode203
Figure 9-29 Control Circuit in Trigger Mode203
Figure 9-30 Control Circuit in Gated Mode204
Timer Synchronization205
6-Step PWM Generation205
Figure 9-31 Control Circuit in Trigger Mode + External Clock Mode2205
Encoder Interface Mode206
Figure 9-32 6-Step PWM Generation, COM Example (OSSR=1)206
Table 9-1 Counting Direction Versus Encoder Signals207
Figure 9-33 Example of Counter Operation in Encoder Interface Mode207
Figure 9-34 Encoder Interface Mode Example with IC1FP1 Polarity Inverted208
Interfacing with Hall Sensor209
Figure 9-35 Example of Hall Sensor Interface210
Timx Register Description(X=1, 8)211
Register Overview211
Table 9-2 Register Overview211
Control Register 1 (Timx_Ctrl1)212
Control Register 2 (Timx_Ctrl2)214
Slave Mode Control Register (Timx_Smctrl)216
Table 9-3 Timx Internal Trigger Connection218
Dma/Interrupt Enable Registers (Timx_Dinten)219
Status Registers (Timx_Sts)220
Event Generation Registers (Timx_Evtgen)222
Capture/Compare Mode Register 1 (Timx_Ccmod1)223
Capture/Compare Mode Register 2 (Timx_Ccmod2)227
Capture/Compare Enable Registers (Timx_Ccen)228
Table 9-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function230
Counters (Timx_Cnt)231
Prescaler (Timx_Psc)231
Auto-Reload Register (Timx_Ar)232
Repeat Count Registers (Timx_Repcnt)232
Capture/Compare Register 1 (Timx_Ccdat1)233
Capture/Compare Register 2 (Timx_Ccdat2)233
Capture/Compare Register 3 (Timx_Ccdat3)234
Capture/Compare Register 4 (Timx_Ccdat4)234
Break and Dead-Time Registers (Timx_Bkdt)235
DMA Control Register (Timx_Dctrl)237
DMA Transfer Buffer Register (Timx_Daddr)237
Capture/Compare Mode Registers 3(Timx_Ccmod3)238
Capture/Compare Register 5 (Timx_Ccdat5)239
Capture/Compare Register 6 (Timx_Ccdat6)239
General-Purpose Timers (TIM3)240
General-Purpose Timers Introduction240
Main Features of General-Purpose Timers240
General-Purpose Timers Description241
Time-Base Unit241
Figure 10-1 Block Diagram of Timx（X=3241
Counter Mode242
Figure 10-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4242
Figure 10-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N243
Figure 9-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1244
Figure 10-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1244
Figure 10-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N245
Figure 10-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N246
Clock Selection247
Figure 10-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)247
Figure 10-8 Control Circuit in Normal Mode, Internal Clock Divided by 1248
Figure 10-9 TI2 External Clock Connection Example249
Figure 10-10 Control Circuit in External Clock Mode 1250
Figure 10-11 External Trigger Input Block Diagram250
Capture/Compare Channels251
Figure 10-12 Control Circuit in External Clock Mode 2251
Figure 10-13 Capture/Compare Channel (Example: Channel 1 Input Stage)252
Figure 10-14 Capture/Compare Channel 1 Main Circuit253
Input Capture Mode254
Figure 10-15 Output Part of Channelx （X = 1,2,3,4;Take Channel 4 as an Example254
PWM Input Mode255
Forced Output Mode256
Output Compare Mode256
Figure 10-16 PWM Input Mode Timing256
PWM Mode258
Figure 10-17 Output Compare Mode, Toggle on OC1258
Figure 10-18 Center-Aligned PWM Waveform (AR=8)259
Figure 10-19 Edge-Aligned PWM Waveform (APR=8)260
One-Pulse Mode261
Figure 10-20 Example of One-Pulse Mode261
Clearing the Ocxref Signal on an External Event262
Debug Mode263
Timx and External Trigger Synchronization263
Timer Synchronization263
Figure 10-21 Control Circuit in Reset Mode263
Figure 10-22 Block Diagram of Timer Interconnection264
Figure 10-23 TIM3 Gated by OC1REF of TIM1265
Figure 10-24 TIM3 Gated by Enable Signal of TIM1266
Figure 10-25 Trigger TIM3 with an Update of TIM1267
Encoder Interface Mode268
Table 10-1 Counting Direction Versus Encoder Signals268
Figure 10-26 Triggers Timers 1 and 3 Using the TI1 Input of TIM1268
Figure 10-27 Example of Counter Operation in Encoder Interface Mode269
Interfacing with Hall Sensor270
Timx Register Description(X=3)270
Register Overview270
Table 10-2 Register Overview270
Control Register 1 (Timx_Ctrl1)272
Control Register 2 (Timx_Ctrl2)274
Slave Mode Control Register (Timx_Smctrl)275
Dma/Interrupt Enable Registers (Timx_Dinten)277
Table 10-3 Timx Internal Trigger Connection277
Status Registers (Timx_Sts)278
Event Generation Registers (Timx_Evtgen)280
Capture/Compare Mode Register 1 (Timx_Ccmod1)281
Capture/Compare Mode Register 2 (Timx_Ccmod2)284
Capture/Compare Enable Registers (Timx_Ccen)286
Counters (Timx_Cnt)287
Table 10-4 Output Control Bits of Standard Ocx Channel287
Prescaler (Timx_Psc)288
Auto-Reload Register (Timx_Ar)288
Capture/Compare Register 1 (Timx_Ccdat1)288
Capture/Compare Register 2 (Timx_Ccdat2)289
Capture/Compare Register 3 (Timx_Ccdat3)289
Capture/Compare Register 4 (Timx_Ccdat4)290
DMA Control Register (Timx_Dctrl)290
DMA Transfer Buffer Register (Timx_Daddr)291
Basic Timers (TIM6)293
Basic Timers Introduction293
Main Features of Basic Timers293
Basic Timers Description293
Time-Base Unit293
Figure 11-1 Block Diagram of Timx（X = 6293
Counter Mode294
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4294
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N295
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1296
Clock Selection297
Debug Mode297
Timx Register Description(X=6)297
Figure 11-5 Control Circuit in Normal Mode, Internal Clock Divided by 1297
Register Overview298
Control Register 1 (Timx_Ctrl1)298
Table 11-1 Register Overview298
Dma/Interrupt Enable Registers (Timx_Dinten)299
Status Registers (Timx_Sts)300
Event Generation Registers (Timx_Evtgen)300
Counters (Timx_Cnt)301
Prescaler (Timx_Psc)301
Automatic Reload Register (Timx_Ar)302
Low Power Timer (LPTIM)303
Introduction303
Main Features303
Block Diagram304
Function Description304
LPTIM Clocks and On-Off Control304
Figure 12-1 LPTIM Diagram304
Prescaler305
Glitch Filter305
Table 12-1 Pre-Scaler Division Ratios305
Timer Enable306
Trigger Multiplexer306
Figure 12-2 Glitch Filter Timing Diagram306
Operating Mode307
Table 12-2 6 Trigger Inputs Corresponding to LPTIM_CFG.TRGSEL[2:0] Bits307
Figure 12-3 LPTIM Output Waveform, Continuous Counting Mode Configuration308
Figure 12-4 PTIM Output Waveform, Single Counting Mode Configuration309
Figure 12-5 LPTIM Output Waveform, Single Counting Mode Configuration and Set-Once Mode Activated309
Waveform Generation310
Register Update311
Figure 12-6 Waveform Generation311
Counter Mode312
Encoder Mode312
Non-Orthogonal Encoder Mode314
Figure 12-7 Encoder Mode Counting Sequence314
Timeout Function315
Figure 12-8 Input Waveforms of Input1 and Input2 When the Decoder Module Is Working Normally315
Figure 12-9 Input1 and Input2 Input Waveforms When Decoder Module Is Not Working315
LPTIM Interrupts316
LPTIM Registers316
LPTIM Register Overview316
LPTIM Interrupt and Status Register (LPTIM_INTSTS)317
LPTIM Interrupt Clear Register (LPTIM_INTCLR)318
LPTIM Interrupt Enable Register (LPTIM_INTEN)319
LPTIM Configuration Register (LPTIM_CFG)320
LPTIM Control Register (LPTIM_CTRL)323
LPTIM Compare Register (LPTIM_COMP)323
LPTIM Auto-Reload Register (LPTIM_ARR)324
LPTIM Counter Register (LPTIM_CNT)324
Independent Watchdog (IWDG)326
Introduction326
Main Features326
Function Description327
Register Access Protection327
Figure 13-1 Functional Block Diagram of the Independent Watchdog Module327
Debug Mode328
User Interface328
Operate Flow328
IWDG Registers329
IWDG Register Overview329
IWDG Key Register (IWDG_KEY)329
Table 13-1 IWDG Counting Maximum and Minimum Reset Time329
Table 13-2 IWDG Register Overview329
IWDG Pre-Scaler Register (IWDG_PREDIV)330
IWDG Reload Register (IWDG_RELV)330
IWDG Status Register (IWDG_STS)331
Window Watchdog (WWDG)332
Introduction332
Main Features332
Function Description332
Figure 14-1 Watchdog Block Diagram332
Timing for Refresh Watchdog and Interrupt Generation333
Figure 14-2 Refresh Window and Interrupt Timing of WWDG333
Debug Mode334
User Interface334
WWDG Configuration Flow334
Table 14-1 Maximum and Minimum Counting Time of WWDG334
WWDG Registers335
WWDG Register Overview335
WWDG Control Register (WWDG_CTRL)335
WWDG Config Register (WWDG_CFG)335
Table 14-2 WWDG Register Overview335
WWDG Status Register (WWDG_STS)336
Analog to Digital Conversion (ADC)337
Introduction337
Main Features337
Function Description338
Table 15-1 ADC Pins338
Figure 15-1 Block Diagram of a Single ADC338
ADC Clock339
ADC Switch Control340
Channel Selection340
Figure 15-2 ADC Clock340
Internal Channel341
Single Conversion Mode341
Continuous Conversion Mode341
Timing Diagram342
Analog Watchdog342
Figure 15-3 Timing Diagram342
Scan Mode343
Injection Channel Management343
Table 15-2 Analog Watchdog Channel Selection343
Discontinuous Mode344
Figure 15-4 Injection Conversion Delay344
Data Aligned345
Programmable Channel Sampling Time345
Table 15-3 Right-Align Data345
Table 15-4 Left-Aligne Data345
Externally Triggered Conversion346
Table 15-5 ADC Is Used for External Triggering of Regular Channels346
Table 15-6 ADC Is Used for External Triggering of Injection Channels346
DMA Requests347
Temperature Sensor347
Temperature Sensor Using Flow348
Figure 15-5 Temperature Sensor and VREFINT Diagram of the Channel348
ADC Interrupt349
OPA Channel Control349
Table 15-7 ADC Interrupt349
Figure 15-6 TIM1 CC4 Triggers OPA Channel Switching ADC Injection Sampling349
Table 15-8 OPA Channel Selection350
ADC Registers351
ADC Register Overview351
Table 15-9 ADC Register Overview351
ADC Status Register (ADC_STS)352
ADC Control Register 1 (ADC_CTRL1)353
ADC Control Register 2 (ADC_CTRL2)355
ADC Sampling Time Register 1 (ADC_SAMPT1)357
ADC Sampling Time Register 2 (ADC_ SAMPT2)358
ADC Sampling Time Register 3 (ADC_SAMPT3)358
ADC Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1360
ADC Watchdog High Threshold Register (ADC_WDGHIGH)360
ADC Watchdog Low Threshold Register (ADC_WDGLOW)360
ADC Regular Sequence Register 1 (ADC_RSEQ1)361
ADC Regular Sequence Register 2 (ADC_RSEQ2)362
ADC Regular Sequence Register 3 (ADC_RSEQ3)362
ADC Injection Sequence Register (ADC_JSEQ)363
ADC Injection Data Register X (Adc_Jdatx) (X= 1364
ADC Regulars Data Register (ADC_DAT)364
ADC Control Register 3 (ADC_CTRL3)365
ADC Test Register (ADC_TEST)366
ADC OPA Control Register (ADC_OPACTRL)366
Comparator (COMP)368
COMP System Connection Block Diagram368
COMP Features368
Figure 16-1 Comparator System Connection Diagram368
COMP Configuration Process369
COMP Working Mode369
Independent Comparator369
Comparator Interconnection370
Interrupt370
COMP Register371
COMP Register Overview371
Table 16-1 COMP Register Overview371
COMP Interrupt Enable Register (COMP_INTEN)372
COMP Interrupt Register (COMP_INTSTS)372
COMP Lock Register(COMP_LOCK)372
COMP Control Register (COMP_CTRL)373
COMP Filter Control Register (COMP_FILC)375
COMP Filter Frequency Division Register (COMP_FILP)375
COMP Reference Input Compare Voltage Register (COMP_INVREF)376
I2C Interface377
Introduction377
Main Features377
Function Description377
SDA and SCL Line Control378
Software Communication Process378
Figure 17-1 I2C Functional Block Diagram379
Start and Stop Conditions379
Figure 17-2 I2C Bus Protocol379
Clock Synchronization and Arbitration379
Figure 17-3 Slave Transmitter Transfer Sequence Diagram382
Figure 17-4 Slave Receiver Transfer Sequence Diagram383
Figure 17-5 Master Transmitter Transfer Sequence Diagram385
Figure 17-6 Master Receiver Transfer Sequence Diagram387
Error Conditions Description388
DMA Application389
Transmit Process389
Receive Process389
Packet Error Check390
Smbus390
Device Identification391
Bus Protocol391
Table 17-1 Comparison between Smbus and I2C391
Address Resolution Protocol392
Debug Mode393
Interrupt Request393
Table 17-2 I 2 C Interrupt Request393
I2C Registers394
I2C Register Overview394
Table 17-3 I2C Register Overview394
I2C Control Register 1 (I2C_CTRL1)395
I2C Control Register 2 (I2C_CTRL2)397
I2C Own Address Register 1 (I2C_OADDR1)398
I2C Own Address Register 2 (I2C_OADDR2)399
I2C Data Register (I2C_DAT)399
I2C Status Register 1 (I2C_STS1)400
I2C Status Register 2 (I2C_STS2)403
I2C Clock Control Register (I2C_CLKCTRL)404
I2C Rise Time Register (I2C_TMRISE)405
Universal Synchronous Asynchronous Receiver Transmitter (USART)407
Introduction407
Main Features407
Functional Block Diagram408
Function Description408
Figure 18-1 USART Block Diagram408
USART Frame Format409
Transmitter410
Figure 18-2 Word Length = 8 Setting410
Figure 18-3 Word Length = 9 Setting410
Table 18-1 Stop Bit Configuration411
Figure 18-4 Configuration Stop Bit411
Single Byte Communication412
Receiver413
Start Bit Detection413
Figure 18-5 TXC/TXDE Changes During Transmission413
Figure 18-6 Start Bit Detection414
Framing Error416
Overrun Error416
Table 18-2 Data Sampling for Noise Detection416
Generation of Fractional Baud Rate417
Receiver's Tolerance Clock Deviation418
Table 18-3 Error Calculation When Setting Baud Rate418
Parity Control419
Table 18-4 When Div_Decimal = 0. Tolerance of USART Receiver419
Table 18-5 When Div_Decimal != 0. Tolerance of USART Receiver419
Table 18-6 Frame Format419
DMA Application420
Figure 18-7 Transmission Using DMA421
Hardware Flow Control422
Figure 18-8 Reception Using DMA422
Figure 18-9 Hardware Flow Control between Two USART423
Figure 18-10 RTS Flow Control423
Multiprocessor Communication424
Idle Line Detection424
Figure 18-11 CTS Flow Controls424
Figure 18-12 Mute Mode Using Idle Line Detection425
Synchronous Mode426
Figure 18-13 Mute Mode Detected Using Address Mark426
Figure 18-14 USART Synchronous Transmission Example427
Figure 18-15 USART Data Clock Timing Example (WL=0)428
Figure 18-16 USART Data Clock Timing Example (WL=1)429
Figure 18-17 RX Data Sampling / Holding Time429
Single-Wire Half-Duplex Mode430
Irda SIR ENDEC Mode430
Irda Low Power Mode431
Figure 18-18 Irdasirendec-Block Diagram431
LIN Mode432
Figure 18-19 Irda Data Modulation (3/16)-Normal Mode432
Figure 18-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)433
Smartcard Mode (ISO7816)434
Figure 18-21 Break Detection and Framing Error Detection in LIN Mode434
Figure 18-22 ISO7816-3 Asynchronous Protocol435
Interrupt Request436
Table 18-7 USART Interrupt Request436
Figure 18-23 Use 1.5 Stop Bits to Detect Parity Errors436
Mode Support437
USART Register437
USART Register Overview437
Table 18-8 USART Mode Setting437
Table 18-9 USART Register Overview437
USART Status Register (USART_STS)438
USART Data Register (USART_DAT)440
USART Baud Rate Register (USART_BRCF)441
USART Control Register 1 Register (USART_CTRL1)441
USART Control Register 2 Register (USART_CTRL2)443
USART Control Register 3 Register (USART_CTRL3)444
USART Guard Time and Prescaler Register (USART_GTP)446
Low Power Universal Asynchronous Receiver Transmitter (LPUART)448
Introduction448
Main Features448
Functional Block Diagram449
Function Description449
Figure 19-1 LPUART Block Diagram449
LPUART Frame Format450
Transmitter450
Figure 19-2 Frame Format450
Receiver452
Figure 19-3 TXC Changes During Transmission452
Fractional Baud Rate Generation454
Table 19-1 Data Sampling for Noise Detection454
Figure 19-4 Data Sampling for Noise Detection454
Parity Control456
DMA Application456
Table 19-2 Parity Frame Format456
Figure 19-5 Sending Using DMA457
Hardware Flow Control458
Figure 19-6 Receiving with DMA458
Figure 19-7 Hardware Flow Control between Two LPUART458
Figure 19-8 RTS Flow Control459
Low Power Wake up460
Interrupt Request460
Table 19-3 LPUART Interrupt Requests460
Figure 19-9 CTS Flow Control460
LPUART Registers461
LPUART Register Overview461
LPUART Status Register (LPUART_STS)461
Table 19-4 LPUART Register Overview461
LPUART Interrupt Enable Register (LPUART_INTEN)462
LPUART Control Register (LPUART_CTRL)463
LPUART Baud Rate Configuration Register 1 (LPUART_BRCFG1)464
LPUART Data Register (LPUART_DAT)465
LPUART Baud Rate Configuration Register 2 (LPUART_BRCFG2)465
LPUART Wake up Data Register (LPUART_WUDAT)466
Serial Peripheral Interface/Inter-IC Sound (SPI/ I2S)467
SPI Introduction467
SPI and I2S Main Features467
SPI Features467
I2S Features467
SPI Function Description468
General Description468
Figure 20-1 SPI Block Diagram468
Figure 20-2 Selective Management of Hardware/Software469
Figure 20-3 Master and Slave Applications470
Data Format471
SPI Work Mode471
Figure 20-4 Data Clock Timing Diagram471
Figure 20-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in472
Figure 20-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode473
Figure 20-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode474
Figure 20-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in475
Figure 20-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional Transmit-Only Mode475
Status Flag477
Figure 20-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted477
Turn off the SPI478
SPI Communication Using DMA479
CRC Calculation480
Figure 20-11 Transmission Using DMA480
Figure 20-12 Reception Using DMA480
Error Flag481
CRC Error (CRCERR)482
SPI Interrupt482
Table 20-1 SPI Interrupt Request482
I2S Function Description483
Figure 20-13 I S Block Diagram483
Supported Audio Protocols484
Figure 20-14 I S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)485
Figure 20-15 I 2 S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)485
Figure 20-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0487
Figure 20-18 MSB Aligns 24-Bit Data, CLKPOL = 0487
Figure 20-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0488
Figure 20-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0488
Figure 20-21 LSB Aligns 24-Bit Data, CLKPOL = 0489
Figure 20-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0489
Figure 20-23 PCM Standard Waveform (16 Bits)490
Figure 20-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)490
Clock Generator491
Figure 20-25 I 2 S Clock Generator Structure491
Figure 20-26 Audio Sampling Frequency Definition491
I2S Send and Receive Sequence492
Table 20-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency492
Status Flag494
Error Flag495
I2S Interrupt495
Table 20-3 I 2 S Interrupt Request495
DMA Function496
SPI and I2S Register Description496
SPI Register Overview496
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)496
Table 20-4 SPI Register Overview496
SPI Control Register 2 (SPI_CTRL2)499
SPI Status Register (SPI_STS)500
SPI Data Register (SPI_DAT)501
SPI CRC Polynomial Register (SPI_CRCPOLY) (Not Used in I2S Mode)501
SPI RX CRC Register (SPI_CRCRDAT) (Not Used in I2S Mode)502
SPI TX CRC Register（Spi_ CRCTDAT502
SPI_ I2S Configuration Register（Spi_I2Scfg503
SPI_I2S Prescaler Register (SPI_I2SPREDIV)504
Real-Time Clock (RTC)506
Description506
Specification506
Table 21-1 RTC Feature Support506
RTC Function Description508
RTC Block Diagram508
Figure 21-1 RTC Block Diagram508
Gpios of RTC509
RTC Register Write Protection509
RTC Clock and Prescaler509
RTC Calendar510
Calendar Initialization and Configuration510
Calendar Reading511
Calibration Clock Output511
Programmable Alarms512
Alarm Configuration512
Alarm Output512
Periodic Automatic Wakeup512
Wakeup Timer Configuration513
Timestamp Function513
Tamper Detection514
Daylight Saving Time Configuration515
RTC Sub-Second Register Shift515
RTC Digital Clock Precision Calibration515
RTC Low Power Mode516
RTC Registers517
RTC Register Overview517
Table 21-2 RTC Register Overview517
RTC Calendar Time Register (RTC_TSH)518
RTC Calendar Date Register (RTC_DATE)518
RTC Control Register (RTC_CTRL)519
RTC Initial Status Register (RTC_INITSTS)521
RTC Prescaler Register (RTC_PRE)524
RTC Wakeup Timer Register (RTC_WKUPT)524
RTC Alarm a Register (RTC_ALARMA)525
RTC Alarm B Register (RTC_ ALARMB)526
RTC Write Protection Register (RTC_WRP)527
RTC Sub-Second Register (RTC_SUBS)527
RTC Shift Control Register (RTC_SCTRL)527
RTC Timestamp Time Register (RTC_TST)528
RTC Timestamp Date Register (RTC_TSD)529
RTC Timestamp Sub-Second Register (RTC_TSSS)529
RTC Calibration Register (RTC_CALIB)530
RTC Tamper Configuration Register（Rtc_Tmpcfg531
RTC Alarm a Sub-Second Register (RTC_ALRMASS)533
RTC Alarm B Sub-Second Register (RTC_ALRMBSS)534
Operational Amplifier (OPAMP)535
OPAMP Features535
Voltage Follower535
OPAMP Function Description535
Figure 22-1 Block Diagram of OPAMP Connection Diagram535
OPAMP Working Mode536
OPAMP Standalone Operational Amplifier Mode536
ADC Channel536
OPAMP Follow Mode537
Figure 22-2 OPAMP Standalone Operational Amplifier Mode537
OPAMP Internal Programmable Gain (PGA) Mode538
Figure 22-3 OPAMP Follow Mode538
OPAMP Independent Write Protection539
OPAMP TIMER Controls the Switching Mode539
Figure 22-4 Internal Programmable Gain Mode539
OPAMP Registers540
OPAMP Register Overview540
OPAMP Control Status Register (OPAMP_CS)540
Table 22-1 OPAMP Register Overview540
OPAMP Lock Register (OPAMP_LOCK)541
Beeper543
Introduction543
Function Description543
Beeper Registers543
Beeper Register Overview543
Beeper Control Register (BEEPER_CTRL)543
Table 23-1 Beeper Register Overview543
Arithmetic Units (HDIV and SQRT)546
Introduction to HDIV and SQRT546
HDIV and SQRT Function Description546
HDIV Registers546
HDIV Register Overview546
Table 24-1 HDIV Register Overview546
HDIV Control Status Register (HDIV_CTRLSTS)547
HDIV Dividend Register (HDIV_DIVIDEND)547
HDIV Divisor Register (HDIV_DIVISOR)548
HDIV Quotient Register (HDIV_QUOTIENT)548
HDIV Remainder Register (HDIV_REMAINDER)548
HDIV Divide by Zero Register (HDIV_DIVBY0)549
SQRT Registers549
SQRT Register Overview549
Table 24-2 SQRT Register Overview549
SQRT Control Status Register (SQRT_CTRLSTS)550
SQRT Radicand Register (SQRT_RADICAND)550
SQRT Square Root Register (SQRT_ROOT)551
Debug Support (DBG)552
Overview552
SWD Function553
Pin Assignment553
Unique Device Serial Number (UID)554
Introduction554
UID Register554
UCID Register554
DBGMCU_ID Register554
Table 26-1 DBGMCU_ID Bit Description554
Version History556
Notice557

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Nations N32G031 Series Specifications

General

Brand	Nations
Model	N32G031 Series
Category	Microcontrollers
Language	English

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