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N32A455 series

32-bit ARM

Cortex

-M4 microcontroller

User manual V1.0.0

Main Page

Table of Contents2
Abbreviations in the Text33
List of Abbreviations for Registers33
Available Peripherals33
Interrupts and Events34
Nested Vectored Interrupt Controller34
Systick Calibration Value Register34
Interrupt and Exception Vectors34
Table 2-1 Vector Table34
External Interrupt/Event Controller (EXTI)37
Introduction37
Main Features37
Functional Description38
Figure 2-1 External Interrupt/Event Controller Block Diagram38
EXTI Line Mapping39
Figure 2-2 External Interrupt GPIO Mapping39
Exti Registers40
EXTI Register Review40
EXTI Interrupt Mask Register (EXTI_IMASK)40
Table 2-2 EXTI Register Review40
EXTI Event Mask Register (EXTI_EMASK)41
Rising Trigger Selection Register (EXTI_RT_CFG)41
Falling Trigger Selection Register (EXTI_FT_CFG)41
EXTI Software Interrupt Event Register (EXTI_SWIE)42
EXTI Pending Register (EXTI_PEND)42
EXTI Timestamp Trigger Source Selection Register (EXTI_TS_SEL)43
Memory and Bus Architecture44
System Architecture44
Bus Architecture44
Figure 3-1 Bus Architecture44
Bus Address Mapping45
Bit Banding46
Figure 3-2 Bus Address Map46
Boot Management47
Memory System48
FLASH Specification48
Table 3-1 List of Boot Mode48
Table 3-2 Flash Bus Address List49
Option Byte52
Table 3-3 Option Byte List53
Write Protect54
Table 3-4 Read Protection Configuration List54
Table 3-5 Flash Read-Write-Erase (1) Permission Control Table56
Icache60
Software Interface60
Sram61
R-Sram（Retention SRAM62
FLASH Register62
Table 3-6 SRAM Capacity Configuration Table62
Table 3-7 FLASH Register Overview63
Power Control (Pwr)72
General Description72
Power Supply72
Power Supply Supervisor74
Figure 4-1 Power Supply Block Diagram74
Figure 4-2 Waveforms of Power-On Reset and Power-Down Reset75
Programmable Voltage Detector (PVD)75
Power Modes76
Table 4-1 Power Modes76
Figure 4-3 PVD Threshold Waveform76
SLEEP Mode80
Enter SLEEP Mode80
Exit SLEEP Mode80
STOP0 Mode81
STOP2 Mode82
STANDBY Mode82
VBAT Mode83
Low-Power Auto-Wakeup（Awu）Mode84
Pwr Registers84
PWR Register Overview84
Table 4-3 PWR Register Overview84
Power Control Register (PWR_CTRL)85
Power Control Status Register(PWR_CTRLSTS)86
Power Control Register 2 (PWR_CTRL2)87
Power Control Register 3 (PWR_CTRL3)88
Backup Registers (Bkp)89
Introduction89
Main Features89
Function Description89
Bkp Registers90
BKP Register Overview90
Table 5-1 BKP Register Overview90
Backup Data Register X (Bkp_Datx) (X = 192
Backup Control Register (BKP_CTRL)92
Backup Control/Status Register (BKP_CTRLSTS)93
Reset and Clock Control (Rcc)95
Reset Control Unit95
Power Reset95
System Reset95
Software Reset96
Low-Power Management Reset96
Backup Domain Reset96
Figure 6-1 System Reset Generation96
Clock Control Unit97
Clock Tree Diagram98
HSE Clock98
Figure 6-2 Clock Tree98
External Crystal/Ceramic Resonator (HSE Crystal)99
HSI Clock99
Figure 6-3 HSE/LSE Clock Source99
PLL Clock100
LSE Clock100
LSI Clock100
System Clock (SYSCLK) Selection101
Clock Security System (CLKSS)101
RTC Clock101
Watchdog Clock102
Clock Output(MCO)102
Rcc Registers102
RCC Register Overview102
Table 6-1 RCC Register Overview102
Clock Control Register (RCC_CTRL)104
Clock Configuration Register (RCC_CFG)105
Clock Interrupt Register (RCC_CLKINT)108
APB2 Peripheral Reset Register (RCC_APB2PRST)110
APB1 Peripheral Reset Register (RCC_APB1PRST)112
AHB Peripheral Clock Enable Register (RCC_AHBPCLKEN)114
APB2 Peripheral Clock Enable Register (RCC_APB2PCLKEN)116
APB1 Peripheral Clock Enable Register (RCC_APB1PCLKEN)118
Backup Domain Control Register (RCC_BDCTRL)121
Clock Control/Status Register (RCC_CTRLSTS)122
AHB Peripheral Reset Register (RCC_AHBPRST)124
Clock Configuration Register 2 (RCC_CFG2)125
Clock Configuration Register 3 (RCC_CFG3)127
Gpio and Afio128
Summary128
I/Ofunction Description129
I/O Mode Configuration129
Table 7-1 I/O Mode and Configuration Relationship129
Figure 7-1 Basic Structure of I/O Port129
Table 7-2 I/O Characteristics of Different I/O Configurations130
Figure 7-2 Input Float/Pull-Up/Pull-Down Configuration131
Figure 7-3 Output Mode Configuration132
Analog Mode133
Figure 7-4 Alternate Function Configuration133
Status after Reset134
Figure 7-5 High Impedance Analog Mode Configuration134
Individual Bit Setting and Bit Clearing135
External Interrupt/Wake-Up Line135
Alternate Function135
Table 7-3 Debug Port Image138
Table 7-4 ADC1 External Trigger Injection Conversion Alternate Function Remapping139
Table 7-5 ADC1 External Trigger Regular Conversion Alternate Function Remapping139
Table 7-6 ADC2 External Trigger Injection Conversion Alternate Function Remapping139
Table 7-7 ADC2 External Trigger Regular Conversion Alternate Function Remapping139
Table 7-8 ADC3 External Trigger Injection Conversion Alternate Function Remapping140
Table 7-9 ADC3 External Trigger Regular Conversion Alternate Function Remapping140
Table 7-10 ADC4 External Trigger Injection Conversion Alternate Function Remapping140
Table 7-11 ADC4 External Trigger Regular Conversion Alternate Function Remapping140
Table 7-12 TIM5 Alternate Function Remapping140
Table 7-13 TIM4 Alternate Function Remapping140
Table 7-14 TIM3 Alternate Function Remapping140
Table 7-15 TIM2 Alternate Function Remapping141
Table 7-16 TIM1 Alternate Function Remapping141
Table 7-17 TIM8 Alternate Function Remapping141
Table 7-18 CAN1 Alternate Function Remapping141
Table 7-19 CAN2 Alternate Function Remapping142
Table 7-20 USART1 Alternate Function Remapping142
Table 7-21 USART2 Alternate Function Remapping142
Table 7-22 USART3 Alternate Function Remapping142
Table 7-23 UART4 Alternate Function Remapping143
Table 7-24 UART5 Alternate Function Remapping143
Table 7-25 UART6 Alternate Function Remapping143
Table 7-26 UART7 Alternate Function Remapping143
Table 7-27 I2C1 Pin Remapping143
Table 7-28 I2C2 Pin Remapping143
Table 7-29 I2C3 Pin Remapping144
Table 7-30 I2C4 Pin Remapping144
Table 7-31 SPI1 Pin Remapping144
Table 7-32 SPI2/I2S2 Pin Remapping144
I/O Configuration of Peripherals145
Table 7-33 SPI3/I2S3 Pin Remapping145
Table 7-34 SDIO Pin Remapping145
Table 7-35 QSPI Pin Remapping145
Table 7-36 ADC/DAC145
Table 7-37 TIM1/TIM8146
Table 7-38 TIM2/3/4/5146
Table 7-39 Bxcan146
Table 7-40 USART146
Table 7-41 I2C147
Table 7-42 SPI147
Table 7-43 I2S147
GPIO Locking Mechanism148
Table 7-45 QSPI148
Table 7-46 Other148
Gpio Registers149
GPIO Register Overview149
GPIO Port Low Configuration Register (Gpiox_Pl_Cfg)150
Table 7-47 GPIO Registers Overview150
GPIO Port High Configuration Register (Gpiox_Ph_Cfg)151
GPIO Port Input Data Register (Gpiox_Pid)152
GPIO Port Output Data Register (Gpiox_Pod)152
GPIO Port Bit Setting/Clearing Register (Gpiox_Pbsc)153
GPIO Port Bit Clear Register (Gpiox_Pbc)153
GPIO Port Lock Configuration Register (Gpiox_Plock_Cfg )154
GPIO Driver Capability Configuration Register (Gpiox_Ds_Cfg )155
GPIO Flip Rate Configuration Register (Gpiox_Sr_Cfg)155
Afio Registers156
AFIO Register Overview156
Table 7-48 AFIO Register Overview156
AFIO Event Control Register (AFIO_ECTRL)157
AFIO Alternate Remap Configuration Register (AFIO_RMP_CFG )157
AFIO External Interrupt Configuration Register 1(AFIO_EXTI_CFG1)161
AFIO External Interrupt Configuration Register 2(AFIO_EXTI_CFG2)161
AFIO External Interrupt Configuration Register 3(AFIO_EXTI_CFG3)162
AFIO External Interrupt Configuration Register 4(AFIO_EXTI_CFG4)163
AFIO Alternate Remapping Configuration Register 3(AFIO_RMP_CFG3)164
AFIO Alternate Remap Configuration Register 4 (AFIO_ RMP_CFG4 )166
AFIO Alternate Remapping Configuration Register 5(AFIO_RMP_CFG5)169
Dma Controller172
Introduction172
Main Features172
Block Diagram173
Function Description173
DMA Operation173
Figure 8-1 DMA Block Diagram173
Channel Priority and Arbitration174
DMA Channels and Number of Transfers174
Programmable Data Bit Width174
Table 8-1 Programmable Data Width and Endian Operation (When PINC = MINC = 1)175
Peripheral/Memory Address Incrementation176
Channel Configuration Procedure176
Flow Control177
Circular Mode177
Table 8-2 Flow Control Table177
Error Management178
Interrupt178
DMA Request Mapping178
Table 8-3 DMA Interrupt Request178
Table 8-4 DMA1 Request Mapping Table for each Channel179
Figure 8-2 DMA1 Request Mapping179
Table 8-5 DMA2 Request Mapping Table for each Channel181
Figure 8-3 DMA2 Request Mapping181
Dma Registers182
DMA Register Overview182
Table 8-6 DMA Register Overview182
DMA Interrupt Status Register (DMA_INTSTS)184
DMA Interrupt Flag Clear Register (DMA_INTCLR)184
DMA Channel X Configuration Register (Dma_Chcfgx)185
DMA Channel X Transfer Number Register (Dma_Txnumx)187
DMA Channel X Peripheral Address Register (Dma_Paddrx)187
DMA Channel X Memory Address Register (Dma_Maddrx)188
DMA1 Channel X Channel Request Select Register (Dma1_Chselx)188
DMA2 Channel X Channel Request Select Register (Dma2_Chselx)190
DMA Channel MAP Enable Register (DMA_CHMAPEN)191
Analog to Digital Conversion (Adc)193
Introduction193
Main Features193
Function Description194
Figure 9-1 Block Diagram of a Single ADC194
ADC Clock195
Table 9-1 ADC Pins195
ADC Switch Control196
Channel Selection196
Figure 9-2 ADC Clock196
Figure 9-3 ADC1 and ADC2 Channel Pin Connections197
Figure 9-4 ADC3 and ADC4 Channel Pin Connections199
Internal Channel200
Single Conversion Mode200
Continuous Conversion Mode200
Timing Diagram201
Analog Watchdog201
Table 9-2 Analog Watchdog Channel Selection201
Figure 9-5 Timing Diagram201
Scanning Mode202
Injection Channel Management202
Discontinuous Mode203
Figure 9-6 Injection Conversion Delay203
Calibration204
Data Aligned204
Figure 9-7 Calibration Sequence Diagram204
Programmable Channel Sampling Time205
Externally Triggered Conversion205
Table 9-3 Right-Align Data205
Table 9-4 Left-Aligne Data205
Table 9-5 External Trigger for Regular Channels of ADC1 and ADC2206
Table 9-6 External Trigger for Regular Channels of ADC3 and ADC4206
Table 9-7 External Trigger for Injection Channel of ADC1 and ADC2206
Dma Requests207
Adc Mode207
Table 9-8 External Trigger for Injection Channel of ADC3 and ADC4207
Independent Mode208
Synchronous Regular Mode208
Figure 9-8 Dual ADC Block Diagram208
Synchronous Injection Mode209
Figure 9-9 Schematic Diagram of Synchronous Regular Mode Conversion of 16 Channels209
Fast Alternate Mode210
Figure 9-10 Schematic Diagram of Synchronous Injection Mode Conversion of 4 Channels210
Slow Alternate Mode211
Figure 9-11 Schematic Diagram of Fast Alternate Mode Conversion for Continuous Conversion of 1 Channel211
Rotation Trigger Mode212
Figure 9-12 Schematic Diagram of Slow Alternate Mode Conversion for 1 Channel212
Figure 9-13 Rotation Triggering: Injecting Channel Groups212
Mixed Synchronous Regular Mode + Synchronous Injection Mode213
Mixed Synchronous Regular Mode + Rotation Trigger Mode213
Figure 9-14 Rotation Trigger: Inject Channel Group in Discontinuous Mode213
Mixed Synchronous Injection Mode + Alternate Mode214
Figure 9-15 Combination of Rotation Mode and Synchronous Regular Mode214
Figure 9-16 Injection Trigger Occurs During Injection Transition214
Temperature Sensor215
Figure 9-17 Alternate Single-Channel Conversions Are Interrupted by Injection Sequences CH3 and CH4215
Temperature Sensor Using Flow216
Adc Interrupt216
Figure 9-18 Temperature Sensor and VREFINT Diagram of the Channel216
Adc Registers217
ADC Register Overview217
Table 9-9 ADC Interrupt217
Table 9-10 ADC Register Overview217
ADC Status Register (ADC_STS)218
ADC Control Register 1 (ADC_CTRL1)219
ADC Control Register 2 (ADC_CTRL2)222
ADC Sampling Time Register 1 (ADC_SAMPT1)224
ADC Sampling Time Register 2 (ADC_ SAMPT2)224
ADC Injected Channel Data Offset Register X (Adc_Joffsetx) (X=1225
ADC Watchdog High Threshold Register (ADC_WDGHIGH)225
ADC Watchdog Low Threshold Register (ADC_WDGLOW)226
ADC Regular Sequence Register 1 (ADC_RSEQ1)226
ADC Regular Sequence Register 2 (ADC_RSEQ2)227
ADC Regular Sequence Register 3 (ADC_RSEQ3)227
ADC Injection Sequence Register (ADC_JSEQ)228
ADC Injection Data Register X (Adc_Jdatx) (X= 1229
ADC Regulars Data Register (ADC_DAT)229
ADC Differential Mode Selection Register (ADC_DIFSEL)229
ADC Calibration Factor (ADC_CALFACT)230
ADC Control Register 3 (ADC_CTRL3)231
ADC Sampling Time Register 3 (ADC_SAMPT3)232
Digital to Analog Conversion (Dac)233
Introduction233
Main Features233
Table 10-1 DAC Pins234
Figure 10-1 Block Diagram of a DAC Channel234
Dac Function Description and Operation Description235
DAC Enable235
DAC Output Buffer235
DAC Data Format235
Figure 10-2 Data Format When DAC Independent Output236
DAC Trigger237
Table 10-2 DAC External Trigger237
Figure 10-3 Data Format for DAC Sync Output237
DAC Conversion238
DAC Output Voltage238
Figure 10-4 Time Diagram of Transitions with Trigger Disabled238
DMA Requests239
Noise Generation239
Figure 10-5 LFSR Algorithm for DAC239
Triangular Wave Generation240
Figure 10-6 DAC Conversion with LFSR Waveform Generation (Enable Software Trigger)240
Figure 10-7 Triangle Wave Generation of DAC240
DAC Dual-Channel Conversion241
Independent Trigger Without Waveform Generator241
Independent Triggers Producing the same Noise241
Figure 10-8 DAC Conversion with Trigonometry Generation (Enable Software Trigger)241
Independent Triggers that Generate Different Noises242
Independent Triggers that Generate the same Triangle Wave242
Independent Trigger to Generate Different Triangle Waves243
Simultaneous Software Startup243
Synchronous Trigger Without Waveform Generator244
Synchronous Triggers that Generate the same Noise244
Synchronous Triggers that Generate Different Noises244
Synchronous Trigger to Generate the same Triangle Wave245
Synchronous Trigger to Generate Different Triangle Waves245
Dac Register246
DAC Registers Overview246
DAC Control Register (DAC_CTRL)246
Table 10-3 DAC Registers Overvie246
DAC Software Trigger Register (DAC_SOTTR)249
Bit Right Aligned Data Hold Register for DAC1 (DAC_DR12CH1)249
Bit Left Aligned Data Hold Register for DAC1 (DAC_DL12CH1)250
8-Bit Right-Aligned Data Hold Register for DAC1 (DAC_DR8CH1)250
Bit Right Aligned Data Hold Register for DAC2 (DAC_DR12CH2)251
Bit Left Aligned Data Hold Register for DAC2 (DAC_DL12CH2)251
8-Bit Right-Aligned Data Hold Register for DAC2 (DAC_DR8CH2)251
Bit Right Aligned Data Hold Register for Dual DAC (DAC_DR12DCH)252
Bit Left Aligned Data Hold Register for Dual DAC (DAC_DL12DCH)252
Bit Right Aligned Data Hold Register for Dual DAC (DAC_DR8DCH)253
DAC1 Data Output Register (DAC_DATO1)253
DAC2 Data Output Register (DAC_DATO2)254
Advanced-Control Timers (Tim1 and Tim8)255
Tim1 and Tim8 Introduction255
Main Features of Tim1 and Tim8255
Tim1 and Tim8 Function Description256
Time-Base Unit256
Figure 11-1 Block Diagram of TIM1 and TIM8256
Prescaler Description257
Counter Mode257
Figure 11-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4257
Up-Counting Mode257
Figure 11-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N258
Down-Counting Mode260
Figure 11-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N260
Center-Aligned Mode260
Figure 11-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N261
Figure 11-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)261
Counter Underflow262
Repetition Counter262
Figure 11-8 Repeat Count Sequence Diagram in Down-Counting Mode263
Figure 11-9 Repeat Count Sequence Diagram in Up-Counting Mode264
Figure 11-10 Repeat Count Sequence Diagram in Center-Aligned Mode264
Clock Selection265
Figure 11-11 Control Circuit in Normal Mode, Internal Clock Divided by 1265
Figure 11-12 TI2 External Clock Connection Example266
Figure 11-13 Control Circuit in External Clock Mode 1267
Figure 11-14 External Trigger Input Block Diagram267
Capture/Compare Channels268
Figure 11-15 Control Circuit in External Clock Mode 2268
Figure 11-16 Capture/Compare Channel (Example: Channel 1 Input Stage)269
Figure 11-17 Capture/Compare Channel 1 Main Circuit270
Input Capture Mode271
Figure 11-18 Output Part of Channelx (X= 1,2,3, Take Channel 1 as Example)271
Figure 11-19 Output Part of Channelx (X= 4)271
PWM Input Mode272
Forced Output Mode273
Figure 11-20 PWM Input Mode Timing273
Output Compare Mode274
PWM Mode275
PWM Center-Aligned Mode275
Figure 11-21 Output Compare Mode, Toggle on OC1275
Figure 11-22 Center-Aligned PWM Waveform (AR=8)276
Figure 11-23 Edge-Aligned PWM Waveform (APR=8)277
One-Pulse Mode278
Clearing the Ocxref Signal on an External Event279
Complementary Outputs with Dead-Time Insertion280
Figure 11-24 Clearing the Ocxref of Timx280
Figure 11-25 Complementary Output with Dead-Time Insertion281
Break Function282
Figure 11-26 Output Behavior in Response to a Break283
Debug Mode284
Timx and External Trigger Synchronization284
Slave Mode: Reset Mode284
Figure 11-27 Control Circuit in Reset Mode284
Slave Mode: Trigger Mode285
Slave Mode: Gated Mode285
Figure 11-28 Control Circuit in Trigger Mode285
Figure 11-29 Control Circuit in Gated Mode286
Timer Synchronization287
6-Step PWM Generation287
Figure 11-30 Control Circuit in Trigger Mode + External Clock Mode2287
Encoder Interface Mode288
Figure 11-31 6-Step PWM Generation, COM Example (OSSR=1)288
Table 11-1 Counting Direction Versus Encoder Signals289
Figure 11-32 Example of Counter Operation in Encoder Interface Mode289
Figure 11-33 Encoder Interface Mode Example with IC1FP1 Polarity Inverted290
Interfacing with Hall Sensor291
Advanced-Control292
Figure 11-34 Example of Hall Sensor Interface292
Timx Register (X=1, 8)293
Register Overview293
Table 11-2 Register Map and Reset Value293
Control Register 1 (Timx_Ctrl1)294
Control Register 2 (Timx_Ctrl2)297
Slave Mode Control Register (Timx_Smctrl)298
Table 11-3 Timx Internal Trigger Connection300
Dma/Interrupt Enable Registers (Timx_Dinten)301
Status Registers (Timx_Sts)302
Event Generation Registers (Timx_Evtgen)304
Capture/Compare Mode Register 1 (Timx_Ccmod1)305
Capture/Compare Mode Register 2 (Timx_Ccmod2)309
Capture/Compare Enable Registers (Timx_Ccen)310
Table 11-4 Output Control Bits of Complementary Ocx and Ocxn Channels with Break Function312
Counters (Timx_Cnt)313
Prescaler (Timx_Psc)313
Auto-Reload Register (Timx_Ar)313
Repeat Count Registers (Timx_Repcnt)314
Capture/Compare Register 1 (Timx_Ccdat1)314
Capture/Compare Register 2 (Timx_Ccdat2)315
Capture/Compare Register 3 (Timx_Ccdat3)315
Capture/Compare Register 4 (Timx_Ccdat4)316
Break and Dead-Time Registers (Timx_Bkdt)316
DMA Control Register (Timx_Dctrl)318
DMA Transfer Buffer Register (Timx_Daddr)319
Capture/Compare Mode Registers 3(Timx_Ccmod3)320
Capture/Compare Register 5 (Timx_Ccdat5)320
Capture/Compare Register 6 (Timx_Ccdat6)321
General-Purpose Timers (Tim2, Tim3, Tim4 and Tim5)322
General-Purpose Timers Introduction322
Main Features of General-Purpose Timers322
General-Purpose Timers Description323
Time-Base Unit323
Figure 12-1 Block Diagram of Timx（X=2, 3 ,4 and 5323
Counter Mode324
Figure 12-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4324
Figure 12-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N325
Figure 11-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1326
Figure 12-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1326
Figure 12-5 Timing Diagram of the Down-Counting, Internal Clock Divided Factor = 2/N327
Figure 12-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2/N328
Clock Selection329
Figure 12-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)329
Figure 12-8 Control Circuit in Normal Mode, Internal Clock Divided by 1330
Figure 12-9 TI2 External Clock Connection Example331
Figure 12-10 Control Circuit in External Clock Mode 1332
Figure 12-11 External Trigger Input Block Diagram332
Capture/Compare Channels333
Figure 12-12 Control Circuit in External Clock Mode 2333
Figure 12-13 Capture/Compare Channel (Example: Channel 1 Input Stage)334
Figure 12-14 Capture/Compare Channel 1 Main Circuit335
Input Capture Mode336
Figure 12-15 Output Part of Channelx （X = 1,2,3,4;Take Channel 4 as an Example336
PWM Input Mode337
Forced Output Mode338
Output Compare Mode338
Figure 12-16 PWM Input Mode Timing338
PWM Mode340
Figure 12-17 Output Compare Mode, Toggle on OC1340
Figure 12-18 Center-Aligned PWM Waveform (AR=8)341
Figure 12-19 Edge-Aligned PWM Waveform (APR=8)342
One-Pulse Mode343
Figure 12-20 Example of One-Pulse Mode343
Clearing the Ocxref Signal on an External Event344
Debug Mode345
Timx and External Trigger Synchronization345
Timer Synchronization345
Figure 12-21 Control Circuit in Reset Mode345
Figure 12-22 Block Diagram of Timer Interconnection346
Figure 12-23 TIM2 Gated by OC1REF of TIM1347
Figure 12-24 TIM2 Gated by Enable Signal of TIM1348
Figure 12-25 Trigger TIM2 with an Update of TIM1349
Encoder Interface Mode350
Table 12-1 Counting Direction Versus Encoder Signals350
Figure 12-26 Triggers Timers 1 and 2 Using the TI1 Input of TIM1350
Figure 12-27 Example of Counter Operation in Encoder Interface Mode351
Interfacing with Hall Sensor352
Timx Register Description(X=2, 3 ,4 and 5)352
Register Overview352
Table 12-2 Register Map and Reset Value352
Figure 12-28 Encoder Interface Mode Example with IC1FP1 Polarity Inverted352
Control Register 1 (Timx_Ctrl1)354
Control Register 2 (Timx_Ctrl2)356
Slave Mode Control Register (Timx_Smctrl)357
Table 12-3 Timx Internal Trigger Connection359
Dma/Interrupt Enable Registers (Timx_Dinten)360
Status Registers (Timx_Sts)361
Event Generation Registers (Timx_Evtgen)362
Capture/Compare Mode Register 1 (Timx_Ccmod1)363
Capture/Compare Mode Register 2 (Timx_Ccmod2)366
Capture/Compare Enable Registers (Timx_Ccen)368
Counters (Timx_Cnt)369
Table 12-4 Output Control Bits of Standard Ocx Channel369
Prescaler (Timx_Psc)370
Auto-Reload Register (Timx_Ar)370
Capture/Compare Register 1 (Timx_Ccdat1)370
Capture/Compare Register 2 (Timx_Ccdat2)371
Capture/Compare Register 3 (Timx_Ccdat3)371
Capture/Compare Register 4 (Timx_Ccdat4)372
DMA Control Register (Timx_Dctrl)372
DMA Transfer Buffer Register (Timx_Daddr)373
Basic Timers (Tim6 and Tim7)375
Introduction375
Main Features375
Basic Timers Description375
Time-Base Unit375
Figure 13-1 Block Diagram of Timx（X = 6 and 7375
Counter Mode376
Figure 13-2 Counter Timing Diagram with Prescaler Division Change from 1 to 4376
Figure 13-3 Timing Diagram of Up-Counting. the Internal Clock Divider Factor = 2/N378
Figure 13-4 Timing Diagram of the Up-Counting, Update Event When ARPEN=0/1379
Clock Selection380
Debug Mode380
Timx Register Description(X = 6 and 7)380
Figure 13-5 Control Circuit in Normal Mode, Internal Clock Divided by 1380
Register Overview381
Control Register 1 (Timx_Ctrl1)381
Table 13-1 Register Overview381
Control Register 2 (Timx_Ctrl2)382
Dma/Interrupt Enable Registers (Timx_Dinten)383
Status Registers (Timx_Sts)384
Event Generation Registers (Timx_Evtgen)384
Counter (Timx_Cnt)385
Prescaler (Timx_Psc)385
Automatic Reload Register (Timx_Ar)385
Real-Time Clock (Rtc)387
Description387
Specification387
Table 14-1 RTC Feature Support387
Rtc Function Description388
RTC Block Diagram388
Figure 14-1 RTC Block Diagram388
Gpios of RTC389
RTC Register Write Protection389
RTC Clock and Prescaler389
RTC Calendar390
Calendar Initialization and Configuration390
Calendar Reading390
Calibration Clock Output391
Programmable Alarms392
Alarm Configuration392
Alarm Output392
Periodic Automatic Wakeup392
Wakeup Timer Configuration393
Timestamp Function393
Daylight Saving Time Configuration393
RTC Sub-Second Register Shift394
RTC Digital Clock Precision Calibration394
RTC Low Power Mode395
Rtc Registers396
RTC Register Overview396
Table 14-2 RTC Register Overview396
RTC Calendar Time Register (RTC_TSH)397
RTC Calendar Date Register (RTC_DATE)397
RTC Control Register (RTC_CTRL)398
RTC Initial Status Register (RTC_INITSTS)400
RTC Prescaler Register (RTC_PRE)402
RTC Wakeup Timer Register (RTC_WKUPT)402
RTC Alarm a Register (RTC_ALARMA)403
RTC Alarm B Register (RTC_ ALARMB)404
RTC Write Protection Register (RTC_WRP)405
RTC Sub-Second Register (RTC_SUBS)405
RTC Shift Control Register (RTC_ SCTRL)406
RTC Timestamp Time Register (RTC_TST)406
RTC Timestamp Date Register (RTC_TSD)407
RTC Timestamp Sub-Second Register (RTC_TSSS)408
RTC Calibration Register (RTC_CALIB)408
RTC Alarm a Sub-Second Register (RTC_ ALRMASS)409
RTC Alarm B Sub-Second Register (RTC_ ALRMBSS)410
RTC Option Register (RTC_ OPT)410
Crc Calculation Unit412
Introduction412
Main Features412
Crc32412
Crc16412
Function Description413
Crc32413
Crc16413
Figure 15-1 CRC Calculation Unit Block Diagram413
Crc Registers414
CRC Register Overview414
CRC32 Data Register (CRC_CRC32DAT)414
CRC32 Independent Data Register (CRC_CRC32IDAT)414
Table 15-1 CRC Register Overview414
CRC32 Control Register (CRC_CRC32CTRL)415
CRC16 Control Register (CRC_CRC16CTRL)415
CRC16 Input Data Register (CRC_CRC16DAT)416
CRC Cyclic Redundancy Check Code Register (CRC_CRC16D)416
LRC Result Register (CRC_LRC)417
Independent Watchdog (Iwdg)418
Introduction418
Main Features418
Functional Description419
Register Access Protection419
Figure 16-1 Functional Block Diagram of the Independent Watchdog Module419
Debug Mode420
User Interface420
Operate Flow420
IWDG Configuration Flow421
Software Flow421
Table 16-1 IWDG Counting Maximum and Minimum Reset Time421
Iwdg Registers422
IWDG Register Overview422
IWDG Key Register (IWDG_KEY)422
IWDG Pre-Scaler Register (IWDG_PREDIV)422
Table 16-2 IWDG Register Overview422
IWDG Reload Register (IWDG_RELV)423
IWDG Status Register (IWDG_STS)424
Window Watchdog (Wwdg)425
Introduction425
Main Features425
Function Description425
Figure 17-1 Watchdog Block Diagram425
Timing for Refresh Watchdog and Interrupt Generation426
Figure 17-2 Refresh Window and Interrupt Timing of WWDG426
Debug Mode427
User Interface427
WWDG Configuration Flow427
Table 17-1 Maximum and Minimum Counting Time of WWDG427
Wwdg Registers428
WWDG Register Overview428
WWDG Control Register (WWDG_CTRL)428
WWDG Config Register (WWDG_CFG)428
Table 17-2 WWDG Register Overview428
WWDG Status Register (WWDG_STS)429
Sdio Interface（Sdio430
Main Features of Sdio430
Sdio Bus Topology431
Figure 18-1 SDIO "No Response" and "No Data" Operations432
Figure 18-2 SDIO (Multi) Data Block Read Operation432
Figure 18-3 SDIO (Multiple) Data Block Write Operation432
Figure 18-4 SDIO Continuous Read Operation432
Sdio Function Description433
SDIO Adapter433
Figure 18-5 SDIO Continuous Write Operation433
Figure 18-6 SDIO Block Diagram433
Figure 18-7 SDIO Adapter434
Adapter Register Block435
Control Unit435
Table 18-1 MMC/SD/SD I/O Card Bus Pin Definition435
Command Unit436
Figure 18-8 Control Unit436
Figure 18-9 SDIO Adapter Command Unit437
Figure 18-10 Command Path State Machine (CPSM)437
Data Channel439
Figure 18-11 SDIO Command Transmission439
Table 18-2 Command Channel Status Flags439
Data Path State Machine (DPSM)440
Figure 18-12 Data Channel440
Figure 18-13 Data Path State Machine (DPSM)441
Table 18-3 Data Token Format442
Table 18-4 Transmit FIFO Status Flags443
Table 18-5 Receive FIFO Status Flags443
SDIO AHB Interface444
Card Function Description445
Confirmation of Working Voltage Range445
Card Reset445
Card Identification Mode446
Card Identification Process446
Write Data Block447
Read Data Block448
Data Streaming Operation (Only for Multimedia Card)448
Erase450
Wide Bus Selection and De-Selection450
Protection Management450
Password Protection451
Table 18-6 Lock/Unlock Data Structure451
Set Password452
Clear Password452
Card Status Register454
Table 18-7 Card Status454
SD Status Register457
Table 18-8 SD Status457
Table 18-9 Speed Type Codes459
Table 18-10 Mobility Performance Codes459
Table 18-11 AU_SIZE Codes459
Table 18-12 Maximum au Size460
Table 18-13 ERASE_SIZE Codes460
Table 18-14 Erase Timeout Code460
SD I/O Mode461
Table 18-15 Erase Offset Codes461
Commands and Responses462
Application Related Commands and General Commands462
Commands of Multimedia Card/Sd Card Module463
Table 18-16 Write Commands for Block-Based Transfers463
Table 18-17 Block-Based Write-Protect Commands464
Table 18-18 Erase Command464
Table 18-19 I/O Mode Command464
Command Type465
Table 18-20 Lock Command465
Table 18-21 Application Related Commands465
Command Format466
Table 18-22 Command Format466
Table 18-23 Short Response Format466
Response Format467
Table 18-24 Long Response Format467
Table 18-25 R1 Response467
Table 18-26 R2 Response468
Table 18-27 R3 Response468
Table 18-28 R4 Response468
Table 18-29 R4B Response469
Table 18-30 R5 Response469
Table 18-31 R6 Response469
Hardware Flow Control470
Sdio Register470
SDIO Register Overview471
Table 18-32 SDIO Register Overview471
SDIO Power Control Register (SDIO_PWRCTRL)472
SDIO Clock Control Register (SDIO_CLKCTRL)472
SDIO Command Argument Register (SDIO_CMDARG)473
SDIO Command Register (SDIO_CMDCTRL)474
SDIO Command Response Register(SDIO_CMDRESP)475
SDIO Response 1475
SDIO Data Timer Register (SDIO_DTIMER)476
Table 18-33 Response Type and Sdio_Responsex Register476
SDIO Data Length Register (SDIO_DATLEN)477
SDIO Data Control Register (SDIO_DATCTRL)477
SDIO Data Counter Register (SDIO_DATCOUNT)479
SDIO Status Register (SDIO_STS)479
SDIO Interrupt Clear Register (SDIO_INTCLR)480
SDIO Interrupt Enable Register (SDIO_INTEN)481
SDIO FIFO Counter Register (SDIO_FIFOCOUNT)484
SDIO Data FIFO Register (SDIO_DATFIFO)485
Controller Area Network (Can)486
Introduction to Can486
Main Features of Can486
Can Overall Introduction486
CAN Module487
CAN Working Mode487
Figure 19-1 Topology of CAN Network487
Normal Mode488
Initialization Mode488
Sleep Mode (Low Power)488
Send Mailbox489
Receiving Filter489
Receive FIFO489
Figure 19-2 CAN Working Mode489
Figure 19-3 Dual CAN Block Diagram490
CAN Test Mode491
Figure 19-4 Loopback Mode491
Figure 19-5 Silent Mode492
Figure 19-6 Loopback Silent Mode492
CAN Debugging Mode493
Can Function Description493
Send Processing493
Cancel Sending494
Time Triggered Communication Mode494
Non-Automatic Retransmission Mode494
Receiving Management495
Figure 19-7 Send Mailbox Status495
Figure 19-8 Receive FIFO Status496
Identifier Filtering497
Mask Mode498
Identifier List Mode498
Figure 19-9 Filter Bit Width Setting-Register Organization498
Table 19-1 Examples of Filter Numbers499
Message Storage500
Figure 19-10 Examples of Filter Mechanisms500
Bit Time Characteristic501
Table 19-2 Send Mailbox Register List501
Table 19-3 Receive Mailbox Register List501
Figure 19-11 Bit Sequence502
Figure 19-12 Various CAN Frames503
Can Interrupt504
Figure 19-13 Event Flag and Interrupt Generation504
Error Management505
Bus-Off Recovery505
Can Configuration Flow505
Figure 19-14 CAN Error State Diagram505
Can Register File507
Register Description507
CAN Register Address Overview508
Table 19-4 CAN Register Overview508
CAN Control and Status Register512
CAN Mailbox Register523
CAN Filter Register528
Serial Peripheral Interface/Inter-IC Sound (Spi/ I 2 S)532
Introduction532
Main Features532
SPI Features532
I 2 S Features532
Spi Function Description533
General Description533
Figure 20-1 SPI Block Diagram533
Figure 20-2 Selective Management of Hardware/Software534
Figure 20-3 Master and Slave Applications535
Data Format536
SPI Work Mode536
Figure 20-4 Data Clock Timing Diagram536
Figure 20-5 Schematic Diagram of the Change of TE/RNE/BUSY When the Host Is Continuously Transmitting in Full Duplex Mode537
Figure 20-6 Schematic Diagram of TE/BUSY Change When the Host Transmits Continuously in One-Way Only Mode538
Figure 20-7 Schematic Diagram of RNE Change When Continuous Transmission Occurs in Receive-Only Mode538
Figure 20-8 Schematic Diagram of the Change of TE/RNE/BUSY When the Slave Is Continuously Transmitting in540
Figure 20-9 Schematic Diagram of TE/BUSY Change During Continuous Transmission in Slave Unidirectional540
Status Flag542
Figure 20-10 Schematic Diagram of TE/BUSY Change When BIDIRMODE = 0 and RONLY = 0 Are Transmitted542
Disabling the SPI543
SPI Communication Using DMA544
Figure 20-11 Transmission Using DMA544
CRC Calculation545
Figure 20-12 Reception Using DMA545
Error Flag546
SPI Interrupt546
Table 20-1 SPI Interrupt Request546
I 2 Sfunction Description547
Figure 20-13 I 2 S Block Diagram547
Supported Audio Protocols548
Figure 20-14 I 2 S Philips Protocol Waveform (16/32-Bit Full Precision, CLKPOL = 0)549
Figure 20-15 I 2 S Philips Protocol Standard Waveform (24-Bit Frame, CLKPOL = 0)549
Figure 20-17 the MSB Is Aligned with 16-Bit or 32-Bit Full Precision, CLKPOL = 0551
Figure 20-18 MSB Aligns 24-Bit Data, CLKPOL = 0551
Figure 20-19 MSB-Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0551
Figure 20-20 LSB Alignment 16-Bit or 32-Bit Full Precision, CLKPOL = 0552
Figure 20-21 LSB Aligns 24-Bit Data, CLKPOL = 0552
Figure 20-22 LSB Aligned 16-Bit Data Is Extended to 32-Bit Packet Frame, CLKPOL = 0553
Clock Generator554
Figure 20-23 PCM Standard Waveform (16 Bits)554
Figure 20-24 PCM Standard Waveform (16-Bit Extended to 32-Bit Packet Frame)554
Figure 20-25 I 2 S Clock Generator Structure555
Figure 20-26 Audio Sampling Frequency Definition555
I 2 S Transmission and Reception Sequence556
Table 20-2 Use the Standard 8Mhz HSE Clock to Get Accurate Audio Frequency556
Master Mode557
Status Flag558
Error Flag559
I 2 S Interrupt559
DMA Function559
Table 20-3 I 2 S Interrupt Request559
Spi and I Sregister560
SPI Register Overview560
SPI Control Register 1 (SPI_CTRL1) (Not Used in I2S Mode)560
Table 20-4 SPI Register Overview560
SPI Control Register 2 (SPI_CTRL2)563
SPI Status Register (SPI_STS)563
SPI Data Register (SPI_DAT)565
SPI CRC Polynomial Register (SPI_CRCPOLY)565
SPI RX CRC Register (SPI_CRCRDAT)565
Mode)565
SPI_ I 2 S Configuration Register （ SPI_I2SCFG566
SPI TX CRC Register SPI_CRCTDAT566
SPI_I S Prescaler Register (SPI_I2SPREDIV)568
I 2 C Interface569
Introduction569
Main Features569
Function Description569
SDA and SCL Line Control569
Software Communication Process570
Start and Stop Conditions571
Figure 21-1 I 2 C Functional Block Diagram571
Figure 21-2 I2C Bus Protocol571
Clock Synchronization and Arbitration572
Figure 21-3 Slave Transmitter Transfer Sequence Diagram574
Figure 21-4 Slave Receiver Transfer Sequence Diagram575
Figure 21-5 Master Transmitter Transfer Sequence Diagram577
Figure 21-6 Master Receiver Transfer Sequence Diagram579
Error Conditions Description580
DMA Application581
Transmit Process581
Receive Process582
Packet Error Check582
Smbus583
Table 21-1 Comparison between Smbus and I2C583
Debug Mode585
Interrupt Request585
Table 21-2 I 2 C Interrupt Request585
I2C Registers586
I2C Register Overview586
Table 21-3 I2C Register Overview586
I2C Control Register 1 (I2C_CTRL1)587
I2C Control Register 2 (I2C_CTRL2)589
I2C Own Address Register 1 (I2C_OADDR1)590
I2C Own Address Register 2 (I2C_OADDR2)591
I2C Data Register (I2C_DAT)591
I2C Status Register 1 (I2C_STS1)592
I2C Status Register 2 (I2C_STS2)595
I2C Clock Control Register (I2C_CLKCTRL)596
I2C Rise Time Register (I2C_TMRISE)597
Universal Synchronous Asynchronous Receiver Transmitter (Usart)598
Introduction598
Main Features598
Functional Block Diagram599
Function Description599
Figure 22-1 USART Block Diagram599
USART Frame Format600
Figure 22-2 Word Length = 8 Setting600
Transmitter601
Table 22-1 Stop Bit Configuration601
Figure 22-3 Word Length = 9 Setting601
Figure 22-4 Configuration Stop Bit602
Single Byte Communication603
Receiver603
Start Bit Detection603
Figure 22-5 TXC/TXDE Changes During Transmission603
Figure 22-6 Start Bit Detection604
Framing Error605
Overrun Error606
Table 22-2 Data Sampling for Noise Detection606
Generation of Fractional Baud Rate606
Table 22-3 Error Calculation When Setting Baud Rate607
Receiver's Tolerance Clock Deviation608
Parity Control608
Table 22-4 When Div_Decimal = 0. Tolerance of USART Receiver608
Table 22-5 When Div_Decimal != 0. Tolerance of USART Receiver608
Table 22-6 Frame Format608
DMA Application609
Figure 22-7 Transmission Using DMA610
Hardware Flow Control611
Figure 22-8 Reception Using DMA611
Figure 22-9 Hardware Flow Control between Two USART611
Figure 22-10 RTS Flow Control612
Figure 22-11 CTS Flow Controls613
Multiprocessor Communication613
Idle Line Detection613
Figure 22-12 Mute Mode Using Idle Line Detection614
Synchronous Mode615
Figure 22-13 Mute Mode Detected Using Address Mark615
Figure 22-14 USART Synchronous Transmission Example616
Figure 22-15 USART Data Clock Timing Example (WL=0)616
Single-Wire Half-Duplex Mode617
Figure 22-16 USART Data Clock Timing Example (WL=1)617
Figure 22-17 RX Data Sampling / Holding Time617
Irda SIR ENDEC Mode618
LIN Mode619
Figure 22-18 Irdasirendec-Block Diagram619
Figure 22-19 Irda Data Modulation (3/16)-Normal Mode619
Figure 22-20 Break Detection in LIN Mode (11-Bit Break Length-The LINBDL Bit Is Set)621
Smartcard Mode (ISO7816)622
Figure 22-21 Break Detection and Framing Error Detection in LIN Mode622
Figure 22-22 ISO7816-3 Asynchronous Protocol623
Interrupt Request624
Table 22-7 USART Interrupt Request624
Figure 22-23 Use 1.5 Stop Bits to Detect Parity Errors624
Mode Support625
Usart Registers625
USART Register Overview625
Table 22-9 USART Register Overview625
USART Status Register (USART_STS)626
USART Data Register (USART_DAT)628
USART Baud Rate Register (USART_BRCF)629
USART Control Register 1 Register (USART_CTRL1)629
USART Control Register 2 Register (USART_CTRL2)631
USART Control Register 3 Register (USART_CTRL3)632
USART Guard Time and Prescaler Register (USART_GTP)634
Quad Serial Peripheral Interface (Qspi)636
Introduction636
Qspi Main Features636
Function Description637
Qspi Command Sequence637
Figure 23-1 QSPI Block Diagram637
Operating Procedures638
QSPI Indirect Mode638
Figure 23-2 QSPI Command Sequence638
QSPI Indirect Send Operation639
QSPI Indirect Receive Operation641
Qspi Register643
QSPI Register Overview643
Table 23-1 QSPI Register Overview643
QSPI Control 0 Register (QSPI_CTRL0)645
QSPI Control 1 Register (QSPI_CTRL1)647
QSPI Enable Register (QSPI_EN)647
QSPI Microwire Control Register (QSPI_MW_CTRL)648
QSPI Slave Enable Register (QSPI_SLAVE_EN)648
QSPI Baud Rate Select Register (QSPI_BAUD)649
QSPI Transmit FIFO Threshold Level Register (QSPI_TXFT)649
QSPI Receive FIFO Threshold Level Register (QSPI_RXFT)650
QSPI Transmit FIFO Level Register (QSPI_TXFN)650
QSPI Receive FIFO Level Register (QSPI_RXFN)651
QSPI Status Register (QSPI_STS)651
QSPI Interrupt Mask Register (QSPI_IMASK)652
QSPI Interrupt Status Register (QSPI_ISTS)653
QSPI Raw Interrupt Status Register (QSPI_RISTS)654
QSPI Transmit FIFO Overflow Interrupt Clear Register (QSPI_TXFOI_CLR)655
QSPI Receive FIFO Overflow Interrupt Clear Register (QSPI_RXFOI_CLR)655
QSPI Receive FIFO Underflow Interrupt Clear Register (QSPI_RXFUI_CLR)655
QSPI Multi-Master Interrupt Clear Register (QSPI_MMCI_CLR)656
QSPI Interrupt Clear Register (QSPI_ICLR)656
QSPI DMA Control Register (QSPI_DMA_CTRL)657
QSPI DMA Transmit Data Level Register (QSPI_DMATDL_CTRL)657
QSPI DMA Receive Data Level Register (QSPI_DMARDL_CTRL)657
QSPI Data Register Qspi_Datx658
QSPI RX Sample Delay Register (QSPI_RS_DELAY)658
QSPI Enhanced SPI Mode Control 0 Register QSPI_ENH_CTRL0659
QSPI DDR Transmit Drive Edge Register (QSPI_DDR_TXDE)660
QSPI XIP Mode Bits Register (QSPI_XIP_MODE)660
QSPI XIP INCR Transfer Opcode Register (QSPI_XIP_INCR_TOC)661
QSPI XIP WRAP Transfer Opcode Register (QSPI_XIP_WRAP_TOC)661
QSPI XIP Control Register (QSPI_XIP_CTRL)662
QSPI XIP Slave Enable Register (QSPI_XIP_SLAVE_EN)663
QSPI XIP Receive FIFO Overflow Interrupt Clear Register (QSPI_XIP_RXFOI_CLR)664
Qspi_Xip_Tout664
Comparator (Comp)666
Comp System Connection Block Diagram666
Figure 24-1 Comparator1 and Comparator2 Connection Diagram666
Figure 24-2 Comparator3 and Comparator4 Connection Diagram667
Figure 24-3 Comparator5,Comparator6,Comparator7 Connection Diagram668
Main Features669
Comp Configuration Process669
Comp Working Mode670
Window Mode670
Independent Comparator670
Comparator Interconnection670
Interrupt671
Comp Register672
COMP Register Overview672
Table 24-1 COMP Register Overview672
COMP Control Register (Compx_Ctrl)674
COMP Window Mode Register (COMP_WINMODE)675
COMP Lock Register (COMP_LOCK)676
COMP Interrupt Enable Register (COMP_INTEN)676
COMP Interrupt Status Register (COMP_INTSTS)677
COMP Filter Register (Compx_Filc)677
COMP Filter Frequency Division Register (Compx_Filp)678
COMP Reference Voltage Register (COMP_VREFSCL)678
Operational Amplifier (Opamp)680
Main Features680
Voltage Follower680
OPAMP Function Description680
Figure 25-1 Block Diagram of OPAMP1 and OPAMP2 Connection Diagram681
Internal Connection between OPAMP and COMP682
Figure 25-2 Block Diagram of OPAMP3 and OPAMP4 Connection Diagram682
Figure 25-3 Simulation Module Linkage Relationship 1683
Figure 25-4 Simulation Module Linkage Relationship 2684
Opamp Working Mode685
OPAMP Independent Op Amp Mode685
OPAMP Follow Mode685
Figure 25-5 OPAMP Standalone Operational Amplifier Mode685
OPAMP Internal Gain (PGA) Mode686
Figure 25-6 Follow Mode686
OPAMP with Filter Internal Gain Mode687
Figure 25-7 Internal Gain Mode687
Figure 25-8 Internal Gain Mode with Filter687
OPAMP Calibration688
OPAMP Independent Write Protection688
OPAMP TIMER Controls the Switching Mode688
Opamp Register688
OPAMP Register Overview688
Table 25-1 OPAMP Register Overview688
OPAMP Control Status Register (Opampx_Cs)689
OPAMP Lock Register (OPAMP_LOCK)691
Debug Support (Dbg)692
Overview692
Figure 26-1 N32A455 Level and Cortex692
Jtag/Swd Function693
Switch JTAG/SWD Interface693
Pin Allocation693
Mcu Debugging Function694
Low Power Mode Support694
Peripheral Debugging Support694
Table 26-1 Debug Port Pin694
Dbg Registers695
DBG Register Overview695
ID Register (DBG_ID)695
Debug Control Register (DBG_CTRL)696
Unique Device Serial Number (Uid)699
Introduction699
Uid Register699
Ucid Register699
Version History700
Notice701

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Nations N32A455 Series Specifications

General

Brand	Nations
Model	N32A455 Series
Category	Microcontrollers
Language	English

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Nations N32A455 Series Specifications

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