Nations N32A455 Series - I2 C Clock Control Register (I2 C_CLKCTRL)

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Nations Technologies Inc.
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Address: Nations Tower, #109 Baoshen Road, Hi-tech Park North.
Nanshan District, Shenzhen, 518057, P.R.China
Bit field
Name
Description
1: when I2C_CTRL1.GCEN=1, general call address was received.
3
Reserved
Reserved, the reset value must be maintained.
2
TRF
Transmitter/receiver
After detecting the stop condition (I2C_STS1.STOPF=1), repeated start condition or bus
arbitration loss (I2C_STS1.ARLOST=1), or when I2C_CTRL1.EN=0, the hardware clears it.
0: Data receiving mode;
1: Data transmission mode;
At the end of the whole address transmission stage, this bit is set according to the R/W bit of
the address byte.
1
BUSY
Bus busy
Hardware clears this bit when a stop condition is detected.
0: No data communication on the bus;
1: Data communication on the bus.
When detecting that SDA or SCL is low level, the hardware sets this bit to' 1';
Note:This bit indicates the bus communication currently in progress, and this information is
still updated when the interface is disabled (I2C_CTRL1.EN=0).
0
MSMODE
Master/slave mode
Hardware clears this bit when a stop condition is detected on the bus, arbitration is lost
(I2C_STS1.ARLOST=1), or when I2C_CTRL1.EN=0.
0: In slave mode;
1: In master mode.
When the interface is in the master mode (I2C_STS1.STARTBF=1), the hardware sets this bit;
21.6.9 I2C Clock control register (I2C_CLKCTRL)
Address offset: 0x1c
Reset value: 0x0000
Note: The CLKCTRL register can only be set when I
2
C is turned off (I2C_CTRL1.EN=0)
Bit field
Name
Description
15
FSMODE
I2C master mode selection
0: I2C in standard mode(duty cycle defaults to 1/1);
1: I2C in fast mode(duty cycle can be configured).
14
DUTY
Duty cycle in fast mode
0：Tlow/Thigh = 2；
1：Tlow/Thigh = 16/9
13:12
Reserved
Reserved, the reset value must be maintained.
11:0
CLKCTRL[11:0]
Clock control register in Fast/Standard mode (Master mode)
This division factor is used to set the SCL clock in the master mode.