Nations N32A455 Series - Figure 11-6 Timing Diagram of the Center-Aligned, Internal Clock Divided Factor =2;N; Figure 11-7 a Center-Aligned Sequence Diagram that Includes Counter Overflows and Underflows (ARPEN = 1)

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Alternatively, an update event can also be generated by setting the TIMx_EVTGEN. UDGN bit (either by software
or using a slave mode controller). In this case, the counter restarts from 0, as does the prescaler's counter.
Please note: if the update source is a counter overflow, auto-reload update before reloading the counter.
Figure 11-6 Timing diagram of the Center-aligned, internal clock divided factor =2/N
Figure 11-7 A center-aligned sequence diagram that includes counter overflows and underflows (ARPEN = 1)
CK_PSC
CNTEN
Timer clock = CK_CNT
Counter register
Update event（UEV）
0003
0002
Counter underflow
Update interrupt flag(UDITF)
0001 0000 0001 0002 0003
CK_PSC
Timer clock = CK_CNT
Counter register
Update event（UEV）
1F20
01 00
Counter underflow
Update interrupt flag(UDITF)
Internal clock
divided by 2
Internal clock divided
by N