NEC MultiSync 4FGe - Page 52

2-3. Self Test Circuit
When the signal cable is disconnected from the video card/computer, pin @ of CN-IN and pin @ of IC851 (CPU)
are set High. Then H sync
(pin a), V sync (pin @) and video (pin 0) compose the CPU generated self test
pattern.
+12V
CN-IN
(
3
I
SELF ID
R D715R
C703G
N
II
0701G
G D715G R706G --G c704G
v--
b+q @ IC701
B D7i5B
R705G
0 A’
II
L
J,
t5v
RKO
r
RI38
4
Ic651
I
CPU @
(5)
$
Ic801
I/F
(Fig 2-3-l) Self Test Circuit
51