The Nokia RH-18/36/38 Series Transceiver is a hand-portable dual-band GSM 900/1800MHz or 850/1900MHz phone, featuring a DCT4 generation baseband (UEM/UPP) and RF (MJOELNER) circuitry. This document focuses on the engine module, which includes the baseband engine chipset, UI components, and acoustical parts.
Environmental Specifications:
- Normal operation: -25°C to +55°C (specifications fulfilled).
- Reduced performance: -40°C to -25°C and +55°C to +85°C.
- No operation and/or storage: < -40°C or > +85°C (attempting to operate may permanently damage the phone).
- Humidity: Relative humidity 5-95%. The module is not protected against water; condensed or splashed water might cause malfunction. Submerging the phone will cause permanent damage. Long-term high humidity with condensation will cause permanent damage due to corrosion.
Technical Summary:
The baseband module contains two main ASICs: the Universal Energy Management (UEM) and the Universal Phone Processor (UPP). It also includes a 16Mbit Flash IC. The baseband is based on the DCT4 engine program. The UEM ASIC primarily manages the interface between the baseband and the RF section, providing A/D and D/A conversion for in-phase and quadrature receive/transmit signals, as well as audio signals to/from the user interface. It supplies analog signals to the RF section under UPP DSP digital control. The RF ASIC MJOELNER is controlled via the UPP RFBUS serial interface, with separate signals for PDM coded audio. Digital speech processing is handled by the DSP within the UPP ASIC. The UEM is a dual-voltage circuit, with digital parts running on 1.8V and analog parts on 2.78V; VBAT is also directly used by some blocks. The baseband supports both internal and external microphone inputs and speaker outputs, with signal source selection and gain control managed by the UEM based on UPP control messages. The transceiver module is built on a 6-layer selective OSP/Gold coated PWB.
Power Management:
The UEM supplies both the baseband and RF modules with regulated voltages of 2.78V and 1.8V. The UEM includes 6 linear LDO regulators for the baseband and 7 for RF. It also supplies the baseband SIM interface with a programmable voltage of either 1.8V or 3.0V. The UPP core is supplied with a programmable voltage of 1.0V, 1.3V, 1.5V, or 1.8V. The UPP operates from a 26MHz clock from the MJOELNER RF ASIC, which is internally divided by two to provide a nominal 13MHz system clock. The DSP and MCU contain PLL clock multipliers. The UEM includes a real-time clock, derived from a 32768Hz crystal oscillator, which is fed to the UPP as a sleep clock.
Communication:
Communication between the UEM and UPP occurs via bi-directional serial buses: CBUS (controlled by MCU at 1MHz) and DBUS (controlled by DSP at 13MHz). Both processors are in the UPP.
Operating Modes:
The baseband has six normal operating modes:
- No_Supply: No supply voltage, due to battery disconnection or low battery. Exited when sufficient battery voltage is detected (VBAT > Vmstr+ or charger connected).
- Power_off: Phone is off but supplied. VRTC regulator is active. RTC status depends on its state when entering this mode.
- Acting_Dead: Phone is off when charger is connected, but powers on without RF parts. Displays charging alert.
- Active: Normal operation, scanning channels, listening to base station, transmitting, and processing information.
- Sleep: MCU and DSP are in stand-by. UEM enters sleep mode when SLEEPX low is detected, putting VCORE, VIO, and VFLASH1 regulators into low quiescent current mode. RF regulators (except VR2) are disabled. Exited by sleep clock counter expiration or external interrupt (charger, key press, headset). Main 26MHz oscillator is shut down; 32kHz sleep clock oscillator is used as reference.
- Charging: Can run in parallel with other modes. Battery type/size is indicated by a BSI resistor. UEM measures battery voltage, temperature, size, and current, controlled by UPP charging software. The CHACON (charging control circuitry) in the UEM controls charging current, limiting battery voltage rise to VBATLim (programmable cut-off limits 3.6V/5.0V/5.25V). Charging current is monitored via voltage drop across a 220mOhm resistor.
Additionally, 'testmode' and 'local mode' exist for product verification.
DC Characteristics (Battery Voltage Ranges):
- VBAT: Min 3.21V, Nom 3.80V, Max 4.39V.
- Charger Input Voltage: -0.3V to 9.2VRMS (16.9Vpeak).
- Vcoff+ (HW off to on): Min 3.0V, Nom 3.1V, Max 3.2V.
- Vcoff- (HW on to off): Min 2.7V, Nom 2.8V, Max 2.9V.
- Vmstr+ (UEM off to on): Min 2.0V, Nom 2.1V, Max 2.2V.
- Vmstr- (UEM on to off): Min 1.8V, Nom 1.9V, Max 2.0V.
- Sw shutdown (In Call): Nom 3.1V.
- Sw shutdown (In Idle): Nom 3.2V.
- GSM devices must work correctly within +/-15% of nominal voltage. UEM hardware shuts down at 3.10V and below. Phone software shuts down at 3.20V for proper shutdown. Nominal voltage is 3.80V. During fast charging, voltages between 4.20V and 4.60V may appear briefly.
Regulators' Voltage Ranges:
- Baseband Regulators (VANA, VFLASH1, VFLASH2, VSIM, VIO, VCORE): Ranges vary, e.g., VANA: Min 2.70V, Nom 2.78V, Max 2.86V. VCORE has multiple programmable levels (e.g., 1.000V to 1.890V).
- RF Regulators (VR1A, VR1B, VR2, VR3, VR4, VR5, VR6, VR7, VBB, VREF2): Ranges vary, e.g., VR1A: Min 4.6V, Nom 4.75V, Max 4.9V. VR2 Vout_on: Min 2.70V, Nom 2.78V, Max 2.86V.
External Signals and Connections:
- System connector (X102):
- VCHAR (Pin 2): Charger positive input. Standard charger (ACP-7) expects 11.1Vpeak (Max 16.9Vpeak, 7.9VRMS, 1.0Apeak). Fast charger expects 7.0VRMS (Max 9.2VRMS, 850mA).
- CHGND (Pin 1): Charger ground.
- External Microphone (MIC2P, MIC2N, MICB2): Differential inputs, 100mVpp, G=20dB. MICB2 (Bias) 2.0-2.25V DC, 600uA external loading.
- External Speaker (XEARP, XEARN): Differential output, 2.0Vpp swing, 154-234W load resistance (2x22Ω + 150Ω), 10nF load capacitance.
- Headset Detection (HookInt, HeadInt): OV to 2.86V (Vflash1). HookInt for call control (UEM AD-converter), HeadInt for accessory detection (UEM AD-converter).
- Battery Connector: 3 contacts: VBAT (voltage terminal, for calibration), GND (ground terminal), BSI (battery size identification, for Flash and local mode forcing). Battery temperature is estimated by an NTC resistor in the Transceiver PWB.
- BSI levels (BL-5C Battery): Normal (75kOhm) for capacity calculation (850mA). Service (3.2-3.4kOhm) for fast power-up in production/R&D/after sales. The battery includes over-temperature and over-voltage protection.
Internal Signals and Connections:
- Internal Microphone (MIC1P, MIC1N, MICB1): Differential inputs, 5mV, G=0dB. MIC1P to MIC1B (RC filtered by 220R/4.7uF). MICB1 (Bias) 2.0-2.25V DC, 600uA external loading. RC filter (220Ω, 4.7μF) provides damping at 217Hz.
- Internal Speaker (EARP, EARN): Differential output, 4.0Vpp swing, 26-32W load resistance, 50nF load capacitance.
Baseband Board Clocks:
- RFCLK: From MJOELNER to UPP, 26MHz (active when SLEEPX is high).
- SLEEPCLK: From UEM to UPP, 32.768KHz (active when VBAT is supplied).
- RFCONVCLK: From UPP to UEM, 13MHz (active when RF converters are active).
- RFBUSCLK: From UPP to MJOELNER, 13MHz (active when bus-enable is active).
- DBUSCLK: From UPP (DSP) to UEM, 13MHz (active when bus-enable is active).
- CBUSCLK: From UPP (MCU) to UEM, 1-1.2MHz (active when bus-enable is active).
- LCDCAMCLK: From UPP (Write) to LCD, 0.3-4MHz. From LCD (Read) to UPP, 0.650-3.25MHz (active when bus-enable is active).
Audio Internal:
- Earpiece: 13mm dynamic earpiece with 32Ω nominal impedance. Placed within C-cover and light guide. Acoustic design involves earmat, A-cover, C-cover, light-guide, and D-cover. C-cover has 5 acoustical holes and a double-sided gasket. Front cover has A-cover and earmat with 6 acoustical holes (2 direct front, 4 leak). Two 10Ω resistors and an EMC filter are in the earpiece circuit for stable output.
- Microphone: Omni-directional, placed in the system connector sealed in a rubber gasket. Sound port in the system connector. Connection includes a differential bias circuit driven from MICB1 bias output with external RC-filters.
- Buzzer: Generates monophonic ringing tones. Electrical interface includes VBATDriv and VSADriv2.
Flashlight:
Used to light up, e.g., a keyhole.
- Nominal current: 20mA (at 25°C), 6mA (at 85°C).
Keyboard:
PWB layout has a grounded outer ring and an inner pad. Power key is integrated in the keypad.
- Configuration: Various UPP pins (GenIO1-27, P00-P15) are configured as inputs with internal pull-up. When a key is pressed, the corresponding line is pulled low, generating an interrupt to the MCU, which then scans the keypad.
- Interrupts: Most keys generate a falling edge interrupt (e.g., GenIOInt5, P0 int, P1 int).
Display & Keyboard Backlight:
- LCD Backlight (RH-18 only): Two side-firing super yellow-green dual pack LEDs on the display FPC illuminate a light guide, distributing light for the LCD and keyboard area.
- Keyboard light: Provided by the LCD backlight; no dedicated keyboard light.
- Display: Black and white 96x65 full dot matrix LCD with a standard DCT4 interface. The LCD cell is part of a module including C-cover, gasket, light guide, spring connector, transflector, LEDs, and earpiece.
Memory Module:
- External burst flash memory: 2Mbyte (16Mbit), optional 4Mbyte (32Mbit) or 8MByte (64Mbit).
- Internal SRAM (in UPP): 2Mbit, optional 4Mbit or 8Mbit (not covered in detail).
SIM Interface:
Located in UPP and UEM. UEM contains power up/down, port gating, card detect, data receiving, ATR-counter, registers, and level shifting buffers logic. It's the electrical interface between the SIM Card and the phone.
Vibra:
Placed at the bottom of the phone. Driven by the UEM (VBATDriv, VSADriv2) via a vibraclk signal.
Test Interfaces:
- Test patterns on engine PWB for service and production.
- Phone HW can be tested via MBUS or FBUS connections using PC software (Phoenix) and production equipment (FLALI/FINUI/LABEL).
- Test points are listed in schematic diagrams.
Connections to Baseband:
- Flash programming: FPS8 box connects to baseband via galvanic connector or test pads. Interface connects flash programmer to UPP via UEM (MBUS, FBUS_TX, FBUS_RX lines) at 2.7V logic level. Uses BSI.
- FBUS Interface: Asynchronous data bus with separate TX/RX signals. Default bit rate 115.2 kbit/s. Used for controlling phone during flashing.
- MBUS Interface: Bi-directional serial bus between phone and PC. Default transmission speed 9.6 kbit/s. Used for controlling phone in service.
General Description of the RF Circuits:
- Receiver signal path: Antenna signal routed to RX/TX switch (Z700). If no control voltage, switch acts as a diplexer. GSM850 signal passes to GSM-RX, GSM1900 to DCS-RX. GSM850 signal routed to SAW filter (Z602) for out-of-band blocking immunity and balanced signal to LNA in Mjoelner (N600). Mjoelner front end has LNA and Pre-Gain amplifier before mixers. Mixer output feeds to Baseband part of Mjoelner (BBAMP, LPF1, DCN1, attenuator, LPF2, DCN2) before feeding to BB for demodulation. GSM1900 chain is similar, with SAW filter Z601.
- Transmitter signal path: I/Q signal from BB routed to modulators for 850/1900MHz. Modulator output terminated in SAW filter (Z603) for GSM850 or balun for GSM1900. Signals amplified in buffers. Amplitude-limited signal amplified in PA (N700) with gain control. TX signal from couplers fed to RX/TX switch to select signal for antenna.
PLL (Phase Locked Loop):
Supplies Local Oscillator (LO) signals for RX/TX mixers. Generates LO-frequencies for EGSM and PCN channels using a synthesizer circuit. All PLL blocks (except VCO, reference X-tal, loop filter) are in the Mjoelner IC.
- Reference frequency: Generated by a 26MHz Voltage Controlled X-tal Oscillator (VCXO) in Mjoelner IC (X-tal is external). 26MHz supplied to BB, divided by 2 in UPP IC for 13MHz BB-clock. Reference frequency supplied to reference divider (RDIV), divided by 65, outputting 400kHz for Phase Detector (φ).
- Feedback control: PLL is a feedback system controlling LO-signal phase and frequency. Includes Phase detector, Charge Pump, Voltage Controlled Oscillator (VCO), N-Divider, and loop filter. VCO (G600) generates single-ended RF output based on control voltage, then differentiated through a balun. Signal fed to Prescaler and N-divider in Mjoelner, dividing frequency by ratio based on selected channel. Divider output to phase detector, compared to 400kHz reference clock. Phase detector controls charge pump to charge/discharge loop filter capacitors, changing VCO control voltage and LO-frequency. PLL keeps LO-frequency locked to 26MHz VCXO. Loop filter components: C639-C641, R618-R619.
- Operation: PLL operates at twice the channel center frequency for PCN TX/RX, and four times for EGSM. Divide-by-2 and divide-by-4 circuits are inserted between PLL output and LO-inputs to PCN/EGSM mixers.
Frequency Plan:
- GSM 850 values:
- Receiver frequency range: 869-894 MHz
- Transmit frequency range: 824-849 MHz
- Duplex spacing: 45 MHz
- Channel spacing: 200 KHz
- Number of RF channels: 174
- Power class: 4 (2 W peak)
- Number of power levels: 15
- GSM 1900 values:
- Receiver frequency range: 1930-1990 MHz
- Transmit frequency range: 1850-1910 MHz
- Duplex spacing: 45 MHz
- Channel spacing: 200 KHz
- Number of RF channels: 374
- Power class: 1 (1 W peak)
- Number of power levels: 16
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