UM10204 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 5 — 9 October 2012 39 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
Arbitration and clock synchronization only take place during the transmission of the
master code and not-acknowledge bit (A
), after which one winning master remains active.
The master code indicates to other devices that an Hs-mode transfer is to begin and the
connected devices must meet the Hs-mode specification. As no device is allowed to
acknowledge the master code, the master code is followed by a not-acknowledge (A
).
After the not-acknowledge bit (A
), and the SCLH line has been pulled-up to a HIGH level,
the active master switches to Hs-mode and enables (at time t
H
, see Figure 34) the
current-source pull-up circuit for the SCLH signal. As other devices can delay the serial
transfer before t
H
by stretching the LOW period of the SCLH signal, the active master
enables its current-source pull-up circuit when all devices have released the SCLH line
and the SCLH signal has reached a HIGH level, thus speeding up the last part of the rise
time of the SCLH signal.
The active master then sends a repeated START condition (Sr) followed by a 7-bit slave
address (or 10-bit slave address, see Section 3.1.11
) with a R/W bit address, and
receives an acknowledge bit (A) from the selected slave.
After a repeated START condition and after each acknowledge bit (A) or not-acknowledge
bit (A
), the active master disables its current-source pull-up circuit. This enables other
devices to delay the serial transfer by stretching the LOW period of the SCLH signal. The
active master re-enables its current-source pull-up circuit again when all devices have
released and the SCLH signal reaches a HIGH level, and so speeds up the last part of the
SCLH signal’s rise time.
Data transfer continues in Hs-mode after the next repeated START (Sr), and only
switches back to F/S-mode after a STOP condition (P). To reduce the overhead of the
master code, it is possible that a master links a number of Hs-mode transfers, separated
by repeated START conditions (Sr).
Fig 33. Data transfer format in Hs-mode
To Next Page
Loading...
