Onkyo TX-7620 - Page 9

TX-—7620
Q107
LM7001 (PLL synthesizer and controller)
FMINo—<d
°
oVDD1
A
Programable
Divider
oVDD2
Shift
Register
»
Latch
34 4t 5) I
CE CL DATA 6801 BO2 B03
Description
Connect to the 7.2 MHz crystal oscillator.
Chip
enable
terminal.
Connect
to
the
PLL
terminal
of
micro
processor.
Serial
clock
input
terminal.
Connect
to
the
CLOCK
terminal
of
micro
processor.
Serial
data
input
terminal.
Connect
to
the
DATA
terminal
of
micro
processor.
FM control signal output terminal. “L”’ when FM.
AM control signal output terminal. ““L” when AM.
AMIN
AM
local
oscillator
input
terminal.
FM local oscillator terminal.
Power supply terminal for back-up.
Power supply terminal.
Charge
pump
output
of
the
phase
detector
which
constitutes
the
PLL.
High
level
is
output
when
the
divided
local
oscillator
frequency
is
high
than
the
reference
frequency.
In
the
opposite
case,
low
level
is
output.
Floating
occurs
when
the
frequencies
matched.
The
output
is
applied
to
the
variable
capacitor
diode
in
the
local
oscillator
through
the
low
pass
filters.