6-12
TECHNICAL DATA Orban Model 6200
IC307. IC300 feeds IC304 and associated components. This stage balances, DC-
biases, and scales the signal to the proper level for the analog-to-digital (A/D)
converter. IC301-B and associated components comprise a servo amp to correctly
DC-bias the signal feeding the A/D converter. R352, R353, R357, and C332 make
an attenuator/RC filter necessary to filter high frequency energy that would oth-
erwise cause aliasing distortion in the A/D converter. The corresponding right
channel circuitry is functionally identical to that just described.
2. Stereo Analog-to-Digital (A/D) Converter
The A/D is a stereo 24-bit sigma-delta converter, implemented on a dual-chip integrated
circuit. The A/D oversamples the audio at 6.144MHz. It applies noise shaping, then it
filters and decimates to a 48kHz sample rate. The samples are output in two's comple-
ment, 32-bit word, two-word frame serial format, MS bit first, and transmitted to the
DSP. The A/D is configured in “Slave Mode” all of its clocks originate from the 6200
system clocking, to interface to the input of the DSP. For more information on 6200 in-
put clocking, please refer to “12.288MHz Oscillator and System Clocking.”
Component-Level Description:
The balanced left analog input is applied to pins 4(+) and 5(−), and the balanced
right analog input is applied to pins 25(+) and 24(−) of the A/D (IC309). The
maximum differential signal that the A/D can accept is typically ±2.45Vpeak. The
A/D samples the left and right inputs simultaneously at 128 times the 6200 sample
rate of 48kHz. MCLK, the master clock input of the A/D (pin 17), is fed a
12.288MHz clock providing the 6.144MHz input sample rate required. The A/D
sends the digitized stereo audio to the first DSP chip (IC700) via its synchronous
serial port formed by the data SDATA (pin 15), the bit clock SCLK (pin 14) and
the word clock LRCK (pin 13).
3. Digital Input Receiver and Sample Rate Converter (SRC)
The digital input receiver accepts digital audio signals using the AES/EBU interface
format (AES3-1992). The receiver and input sample rate converter (SRC) together will
accept and sample-rate convert any of the “standard” 32kHz, 44.1kHz, 48kHz rates in
addition to any digital audio sample rate within the range of 25kHz and 55kHz. The au-
dio signal received is decoded by the AES receiver and sent to the SRC. The SRC con-
verts the input sample rate to the 48kHz 6200 system sample rate. Via a synchronous
serial interface, the SRC sends the 48kHz sample rate audio to the DSP for processing.
Component-Level Description:
The differential digital input signal is received through a shielded 1:1 pulse trans-
former (T600). T600 has very low inter-winding capacitance, providing a high
level of isolation for high frequency common mode interference. IC600 is a dedi-
cated AES/EBU digital audio receiver integrated circuit. It contains a phase
locked loop that recovers the clock and the synchronization information present in
the AES/EBU signal. A Schmitt trigger at the input provides 50mV of hysteresis
for added noise immunity. R604 provides a 110Ω input impedance per the
AES/EBU specification.
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