Panasonic DMR-PWT550GL - Digital P.C.B. Block Diagram (2;2)

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11.4. Digital P.C.B. Block Diagram (2/2)
IC51001
(HD DEC/ ENC/ CPU/ GFX /DDR3-IF/RTSC/AV Core/Graphics)
Process
L55001
L55002
JK55001
1
3
4
6
7
9
10
12
D2+
D2-
D1+
D1-
D0+
D0-
CLK+
CLK-
16
15
HDMISDA
HOTPLG
HDMISCL
HDMI JACK
13
CEC
19
FROM/TO TIMER BLOCK DIAGRAM
DIGITAL BLOCK DIAGRAM(2/2)
DMR-PWT550GL/GZ
VIDEO REC SIGNAL
VIDEO EE SIGNAL
VIDEO PB SIGNAL
AUDIO REC SIGNAL
AUDIO EE SIGNAL
AUDIO PB SIGNAL
HTTX2P
HTTX2M
HTTX1P
HTTX1M
HTTX0P
HTTX0M
HTTXCP
HTTXCM
PORT20
HTSDA
HTSCL
NDTXA
AP17
DTXA
AN17
DRXA
NDRXA
AM16
3
TX-
TX+
RX+
RX-
6
5
2
4
3
P58815
DRIVE
PEAKS-ProS-ATA
1
2
L56003
4
3
1
2
L56004
AN16
DTXB
AP15
NDTXB
AN15
NDRXB
DRXB AN14
5
TXP
TXN
RXP
RXN
2
3
6
4
3
P58807
HDD
1
2
L56001
AP14
SD0DAT0
SD0DAT1
SD0DAT2
SD0DAT3
AE5
AE6
AF5
AG6
SD0CLK
SD0CMD
SD0WP
SD0CD
AE7
AF6
AD5
AC5
DAT0
7
8
9
1
5
2
WP
CD
DAT1
DAT2
DAT3
CLK
CMD
WP
CD
P56101
(SD CARD SLOT)
W32
W33
V33
V34
U33
U34
T32
T33
AG31
R31
R34
X51201
AXI
AXO
Y34
AA34
1
3
JK54002
AO2IEC
AP18