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Panasonic FP-E - Page 276

Panasonic FP-E
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High−level Instructions
3 − 12
Outline Inverts 16-bit data and transfers it to the specified 16-bit area.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P2 (PMV/)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F2 MV/ , DT 11 , DT 20
S
D
R0
Trigger
10
11
ST R 0
F 2 (MV/)
DT 11
DT 20
S 16-bit equivalent constant or 16-bit area to be inverted (source)
D 16-bit area (destination)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX (*3) IY (*4) K H
Index
modifier
S A A A A A A A A A A A A A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
The contents of data register DT11 are inverted and transferred to data register DT20 when trigger R0 turns
on.
DT 20
DT 21
DT 22
DT 10
DT 11
DT 12
DT 20
DT 21
DT 22
····
Bit position
·····
DT11
15
010
12
1
11
010
8
1
7
010
4
1
3
010
0
1
Source [S]: H5555
····
Bit position
·····
DT20
15
101
12
0
11
101
8
0
7
101
4
0
3
101
0
0
Destination [D]: HAAAA
H 23AH 5555
H3F
H 1234
[S]
H 1111
H FFFF
[D]
H 23AH 5555
H3F
H 1234
[S]
H AAAA
H FFFF
[D]
Invert and
transfer
R0: on “F2 (MV/)” execution
DT 10
DT 11
DT 12
Invert and transfer
F2
P2
16-bit data invert and move
(MV/)
(PMV/)
A: Available
N/A: Not Available
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