Panasonic FP-E - Page 331

High−level Instructions
3 − 67
Outline Subtracts 16-bit data from the minuend.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P25 (P−)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F25 −, DT 10 , DT 20
S
D
Trigger
R0
10
11
ST R 0
F25 (− )
DT 10
DT 20
S 16-bit equivalent constant or 16-bit area (for subtrahend)
D 16-bit area (for minuend and result)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
S A A A A A A A A A A A A A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Subtracts the contents of data register DT10 from the contents of data register DT20 when trigger R0 turns
on.
Example 1: When the decimal number 16 is in DT20 and the decimal number
4 is in DT10.
000 0000000010000
DT20
000 0000000000100
DT10
D: K16
S:
−
K4
=
000 0000000001100
DT20
D:
K12
(Subtraction)
F25
P25
(−)
(P−)
16-bit data subtraction
[D − S → D]
A: Available
N/A: Not Available
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