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Panasonic FP-E - Page 333

Panasonic FP-E
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High−level Instructions
3 − 69
Outline Subtracts 32-bit data from the minuend.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P26 (PD−)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F26 D− , DT 10 , DT 20
S
D
Trigger
R0
10
11
ST R 0
F26 (D−)
DT 10
DT 20
S 32-bit equivalent constant or lower 16-bit area of 32-bit area (for subtrahend)
D Lower 16-bit area of 32-bit data (for minuend and result)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
S A A A A A A A A A A N/A A A A
D N/A A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
F26
P26
(D−)
(PD−)
32-bit data subtraction
[(D+1, D) − (S+1, S) → (D+1, D)]
A: Available
N/A: Not Available
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