Panasonic FP-E - Page 351

High−level Instructions
3 − 87
Outline Adds 1 to 32-bit data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P36 (PD+1)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F36 D+1 , DT 0
D
Trigger
R0
10
11
ST R 0
F 36 (D+1)
DT 0
D Lower 16-bit area of 32-bit data to be increased by 1
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
D N/A A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Adds 1 to the content of data registers DT1 and DT0 when trigger R0 turns on.
Contents of
DT1
Higher 16 bits Lower 16 bits
Contents of
DT0
+1
Store to DT1 Store to DT0
The specified data area and the
following data area are handled
together as 32−bit data.
F36
P36
(PD+1)
(D+1)
32-bit data increment
[(D + 1, D) + 1 → (D + 1, D)]
A: Available
N/A: Not Available
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