Panasonic FP-E - Page 355

High−level Instructions
3 − 91
Outline Subtracts 1 from 32-bit data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P38 (PD−1)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F38 D−1 , DT 0
R0
D
Trigger
10
11
ST R 0
F38 (D−1)
DT 0
D Lower 16-bit area of 32-bit data to be decreased by 1
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY K H
Index
modifier
D N/A A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
Explanation of example
Subtracts 1 from the content of data registers DT1 and DT0 when trigger R0 turns on.
Higher 16 bits Lower 16 bits
−1
Contents of
DT1
Contents of
DT0
Store to DT1 Store to DT0
The specified data area and the
following data area are handled
together as 32−bit data.
F38
P38
(PD−1)
(D−1)
32-bit data decrement
[(D+1, D) − 1 → (D+1, D)]
A: Available
N/A: Not Available
Phone: 800.894.0412 - Fax: 888.723.4773 - Web: www.clrwtr.com - Email: info@clrwtr.com