Panasonic FP-E - Page 357

High−level Instructions
3 − 93
Outline Multiplies two 32-bit data items and stores the result in the specified
32-bit area.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P39 (PD*D)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
F39 D*D, DT 10, DT 20, DT 3010
R0
S2 DS1
Trigger
10
11
ST R 0
F39 (D*D)
DT 10
DT 20
DT 30
S1 32-bit equivalent constant or lower 16-bit area of 32-bit data (for multiplicand)
S2 32-bit equivalent constant or lower 16-bit area of 32-bit data (for multiplier)
D Lower 16-bit area of 32-bit data (for result)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Inte
g
er
Operand
WX WY WR WL SV EV DT LD
FL
(*1)
I K H f
Index
modifier
Integer
device
S1 A A A A A A A A A A A A N/A A N/A
S2 A A A A A A A A A A A A N/A A N/A
D N/A A A A A A A A A N/A N/A N/A N/A A N/A
(*1) This cannot be used with the FP0R, FPΣ and FP−X.
Explanation of example
Multiplies the contents of data registers DT11 and DT10 and the contents of data registers DT21 and DT20
when trigger R0 turns on. The multiplied result is stored in data registers DT31 and DT30.
DT11
DT20DT21
16 bits 16 bits
DT10
DT31 DT30
16 bits 16 bits
16 bits 16 bits
R0: on
F39
P39
(PD*D)
(D*D)
32-bit data multiplication
(result in 32 bits)
A
:
A
vailable
N/A: Not Available
Phone: 800.894.0412 - Fax: 888.723.4773 - Web: www.clrwtr.com - Email: info@clrwtr.com