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Panasonic FP-E - Page 379

Panasonic FP-E
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High−level Instructions
3 − 115
Outline Divides one BCD data item that expresses a 4-digit decimal number
(4-digit BCD H code) by another (divisor).
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P52 (PB%)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F52 B% , DT10 , DT20 , DT30
S1
D
Trigger
S2
R0
10
11
ST R 0
F 52 (B%)
DT 10
DT 20
DT 30
S1 4-digit BCD equivalent constant or 16-bit area for BCD data (for dividend)
S2 4-digit BCD equivalent constant or 16-bit area for BCD data (for divisor)
D 16-bit area for BCD data (for quotient)
(Remainder is stored in special data register DT9015 or DT90015.)
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
S1 A A A A A A A A A A A K A A
S2 A A A A A A A A A A A K A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
F52
P52
(PB%)
(B%)
4-digit BCD data division
[S1/S2 → D… (DT9015) or (DT90015)]
A: Available
N/A: Not Available
K: K0 to K9
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