Panasonic FP-E - Page 389

High−level Instructions
3 − 125
Outline Subtracts 1 from BCD data that expresses an 8-digit decimal number
(8-digit BCD H code).
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P58 (PDB−1)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F58 DB−1 , DT 0
D
Trigger
R0
10
11
ST R 0
F 58 (DB−1)
DT 0
D Lower 16-bit area for 8-digit BCD data to be decreased by 1
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY
(*4)
K H
Index
modifier
D N/A A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
Explanation of example
Subtracts 1 from the contents (8 −digit BCD data) of data registers DT1 and DT0 when trigger R0 turns on.
Higher 16 bits Lower 16 bits
−1
Contents of
DT1
Contents of
DT0
Store to DT1 Store to DT0
The specified data area and the
following data area are handled
together as 32−bit data.
F58
P58
(PDB−1)
(DB−1)
8-digit BCD data decrement
[(D+1, D) − 1 → (D+1, D)]
A: Available
N/A: Not Available
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