High−level Instructions
3 − 143
Outline Performs bit-wise AND operation on two 16-bit data items.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level ainstruction
“P65 (PWAN)” is not available.
Program example
Boolean
Ladder Diagram
Address Instruction
10
F65 WAN , DT10 , DT 20, DT30
S1
D
Trigger
S2
R0
10
11
ST R 0
F 65 (WAN)
DT 10
DT 20
DT 30
S1 16-bit equivalent constant or 16-bit area
S2 16-bit equivalent constant or 16-bit area
D 16-bit area for storing AND operation result
Operands
modifier
S1 A A A A A A A A A A A A A A
S2 A A A A A A A A A A A A A A
D N/A A A A A A A A A A A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
(*4) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is ID.
Explanation of example
Performs AND operation on each bit in data registers DT10 and DT20 when trigger R0 turns on.
The AND operation result is stored in data register DT30.
[S1]
[S2]
[D]
····
Bit position
·····
DT10
15
010
12
0
11
110
8
1
7
101
4
1
3
100
0
1
R0: on
····Bit position ·····
DT20
15
000
12
0
11
000
8
0
7
111
4
1
3
111
0
1
····Bit position ·····
DT30
15
000
12
0
11
000
8
0
7
101
4
1
3
100
0
1
F65
P65
(PWAN)
(WAN)
16-bit data AND
A: Available
N/A: Not Available
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