Panasonic FP-E - Page 460

High−level Instructions
3 − 196
Outline Takes complement of 2 in 32-bit data.
For the FP0R/FPΣ/FP−X/FP0/FP−e, the P type high−level instruction
“P86 (PDNEG)” is not available.
Program example
Ladder
Diagram
Boolean
Ladder Diagram
Address Instruction
10
F86 DNEG , DT 0
D
Trigger
R20
10
11
ST R 20
F 86 (DNEG)
DT 0
D Lower 16-bit area of 32-bit data for storing original data and its two’s
complement
Operands
Operand
Relay Timer/Counter Register
Index
register
Constant
Inde
x
Operand
WX WY WR
WL
(*1)
SV EV DT
LD
(*1)
FL
(*2)
IX
(*3)
IY K H
Index
modifier
D N/A A A A A A A A A A N/A N/A N/A A
(*1) This cannot be used with the FP0 and FP−e.
(*2) This cannot be used with the FP0, FP−e, FP0R, FPΣ, FP−X.
(*3) With the FP0R, FPΣ,FP−X, FP2, FP2SH, and FP10SH, this is I0 to IC.
Explanation of example
Takes two’s complement of data registers DT1 and DT0 when trigger R20 turns on.
····
Bit position
·····
Binary data
15
0
1211
00
8
0
7
00
4
0
3
0
0
R20: on
Destination
Decimal data
·········
15
0
12
0
11
0
8
0
7
0
4
0
3
01
0
1
Higher 16-bit area Lower 16-bit area
DT1 DT0
····
Bit position
·····
Binary data
15
1
1211
11
8
1
7
11
4
1
3
1
0
Destination
Decimal data
·········
15
1
12
1
11
1
87
1
4
1
3
10
0
1
Higher 16-bit area Lower 16-bit area
DT1 DT0
1111111111111111
K−3
000000000000000
K3
F86
P86
(PDNEG)
(DNEG)
32-bit data complement of 2
A: Available
N/A: Not Available
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